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1. 发明授权

US07768112B2 Semiconductor package fabricated by cutting and molding in small windows 有权
标题翻译：通过在小窗口中切割和成型制造的半导体封装
公开(公告)号：US07768112B2
公开(公告)日：2010-08-03
申请号：US12542304
申请日：2009-08-17
申请人： Kuo-Yuan Lee , Yung-Hsiang Chen
发明人： Kuo-Yuan Lee , Yung-Hsiang Chen
IPC分类号： H01L23/02 , H01L23/48 , H01L23/52 , H01L29/40 , H01L23/28
CPC分类号： H01L21/561 , H01L23/3128 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/49 , H01L2224/73215 , H01L2224/92 , H01L2224/92147 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A method for cutting and molding in small windows of a window-type semiconductor package and the semiconductor package fabricated from the same are revealed. According to the method, a substrate strip has a plurality of small windows disposed at the sides or at the corners of the substrate strip. The external surface of the substrate strip includes a plurality of window molding areas surrounding the small windows and extending to the scribe lines. A plurality of chips are disposed on the substrate strip. Then, an encapsulant is formed in the small windows to encapsulate the electrical connecting components and formed on the window molding areas so that the encapsulant extends to the scribe lines. Therefore, the mold flashes at the small windows can be effectively reduced. Additionally, the encapsulant on the window molding areas is cut when singulating the substrate units so that the adhesion area of the encapsulant to the substrate strip is increased to prevent the delamination of traces and solder mask of the substrate units.
摘要翻译：揭示了一种在窗型半导体封装的小窗口中切割和模制的方法以及由其制造的半导体封装。根据该方法，衬底条具有设置在衬底条的侧面或拐角处的多个小窗口。衬底条的外表面包括围绕小窗口并延伸到划线的多个窗口模制区域。多个芯片设置在基板条上。然后，在小窗口中形成密封剂以封装电连接部件并形成在窗口成型区域上，使得密封剂延伸到划线。因此，模具在小窗口闪烁可以有效降低。此外，当单个衬底单元时，在窗口成型区域上的密封剂被切割，使得密封剂与衬底带的粘合面积增加以防止衬底单元的迹线和焊接掩模的分层。

2. 发明授权

US08361841B2 Mold array process method to encapsulate substrate cut edges 有权
标题翻译：模具阵列法封装衬底切割边缘
公开(公告)号：US08361841B2
公开(公告)日：2013-01-29
申请号：US13093476
申请日：2011-04-25
申请人： Kuo-Yuan Lee , Yung-Hsiang Chen , Wen-Chun Chiu
发明人： Kuo-Yuan Lee , Yung-Hsiang Chen , Wen-Chun Chiu
IPC分类号： H01L21/00
CPC分类号： H01L24/97 , H01L24/73 , H01L2224/32013 , H01L2224/32225 , H01L2224/48227 , H01L2224/4824 , H01L2224/50 , H01L2224/73215 , H01L2224/73265 , H01L2224/97 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/00012 , H01L2224/85 , H01L2924/00
摘要： Disclosed is a mold array process (MAP) method to encapsulate cut edges of substrate units. A substrate strip includes a plurality of substrate units arranged in a matrix. Scribe lines are defined between adjacent substrate units and at the peripheries of the matrix where pre-cut grooves are formed along the scribe lines with a width greater than the width of the scribe lines. An encapsulant is formed on the matrix of the substrate strip to continuously encapsulate the substrate units and the scribe lines to enable the encapsulant to fill into the pre-cut grooves to further encapsulate the cut edges of the substrate units. The cut edges of the substrate units are still encapsulated by the encapsulant even after singulation processes where substrate units are singulated into individual semiconductor packages to prevent the exposure of the plated traces of the substrate units to enhance the moisture resistance capability of the semiconductor packages.
摘要翻译：公开了一种用于封装基板单元的切割边缘的模具阵列工艺（MAP）方法。衬底条包括布置成矩阵的多个衬底单元。划线在相邻的基板单元之间以及在矩形的周边处被限定，其中沿着划线形成预切割槽，其宽度大于划线的宽度。在衬底条的矩阵上形成密封剂以连续地包封衬底单元和划痕线，以使密封剂能够填充到预切割凹槽中以进一步封装衬底单元的切割边缘。衬底单元的切割边缘即使在将衬底单元划分成单个半导体封装的单独处理之后仍然被密封剂封装，以防止衬底单元的电镀迹线的暴露，以增强半导体封装的耐湿性能。

3. 发明授权

US07723157B2 Method for cutting and molding in small windows to fabricate semiconductor packages 有权
标题翻译：用于在小窗户中切割和模制以制造半导体封装的方法
公开(公告)号：US07723157B2
公开(公告)日：2010-05-25
申请号：US12003634
申请日：2007-12-28
申请人： Kuo-Yuan Lee , Yung-Hsiang Chen
发明人： Kuo-Yuan Lee , Yung-Hsiang Chen
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/561 , H01L23/3128 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/49 , H01L2224/73215 , H01L2224/92 , H01L2224/92147 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A method for cutting and molding in small windows of a window-type semiconductor package and the semiconductor package fabricated from the same are revealed. According to the method, a substrate strip has a plurality of small windows disposed at the sides or at the corners of the substrate strip. The external surface of the substrate strip includes a plurality of window molding areas surrounding the small windows and extending to the scribe lines. A plurality of chips are disposed on the substrate strip. Then, an encapsulant is formed in the small windows to encapsulate the electrical connecting components and formed on the window molding areas so that the encapsulant extends to the scribe lines. Therefore, the mold flashes at the small windows can be effectively reduced. Additionally, the encapsulant on the window molding areas is cut when singulating the substrate units so that the adhesion area of the encapsulant to the substrate strip is increased to prevent the delamination of traces and solder mask of the substrate units.
摘要翻译：揭示了一种在窗型半导体封装的小窗口中切割和模制的方法以及由其制造的半导体封装。根据该方法，衬底条具有设置在衬底条的侧面或拐角处的多个小窗口。衬底条的外表面包括围绕小窗口并延伸到划线的多个窗口模制区域。多个芯片设置在基板条上。然后，在小窗口中形成密封剂以封装电连接部件并形成在窗口成型区域上，使得密封剂延伸到划线。因此，模具在小窗口闪烁可以有效降低。此外，当单个衬底单元时，在窗口成型区域上的密封剂被切割，使得密封剂与衬底带的粘合面积增加以防止衬底单元的迹线和焊接掩模的分层。

4. 发明申请

US20120264257A1 MOLD ARRAY PROCESS METHOD TO PREVENT EXPOSURE OF SUBSTRATE PERIPHERIES 审中-公开
标题翻译：模板周转过程防止曝光的方法
公开(公告)号：US20120264257A1
公开(公告)日：2012-10-18
申请号：US13086851
申请日：2011-04-14
申请人： Kuo-Yuan Lee , Yung-Hsiang Chen , Wen-Chun Chiu
发明人： Kuo-Yuan Lee , Yung-Hsiang Chen , Wen-Chun Chiu
IPC分类号： H01L21/56
CPC分类号： H01L23/3128 , H01L21/561 , H01L21/565 , H01L23/13 , H01L23/49816 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/50 , H01L24/73 , H01L24/86 , H01L24/97 , H01L2224/0401 , H01L2224/04042 , H01L2224/06156 , H01L2224/1624 , H01L2224/2919 , H01L2224/32014 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4824 , H01L2224/50 , H01L2224/73203 , H01L2224/73215 , H01L2224/73219 , H01L2224/92147 , H01L2224/97 , H01L2924/00013 , H01L2924/01029 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/1515 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2224/85 , H01L2224/86 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： Disclosed is a mold array process (MAP) method to prevent exposure of peripheries of substrate units where the major characteristic is to implement two kinds of encapsulating materials in the MAP method in mass production. A first encapsulating material for encapsulating chips is formed on a substrate strip by molding to continuously encapsulate the substrate units and the scribe lines between adjacent substrate units. Prior to forming a second encapsulating material, a plurality of cut grooves are formed along the scribing lines by pre-cutting processes to penetrate through the substrate strip but without penetrating through the first encapsulating material and have such a width that a plurality of peripheries of the substrate units are exposed outside the scribing lines. Then, the second encapsulating material is filled into the cut grooves. Accordingly, the peripheries of the substrate units are still encapsulated with the remains of the second encapsulating material after singulation processes where the substrate units are singulated into individual semiconductor packages to prevent exposure of the peripheries of the substrate units.
摘要翻译：公开了一种模具阵列工艺（MAP）方法，用于防止在大规模生产中在MAP方法中实现两种封装材料的基板单元周围的暴露。用于封装芯片的第一封装材料通过模制而形成在衬底条上，以将衬底单元和划线连续封装在相邻衬底单元之间。在形成第二封装材料之前，通过预切割工艺沿着划刻线形成多个切割槽，以穿透衬底条而不穿透第一封装材料，并且具有这样的宽度：多个外围的衬底单元暴露在划线之外。然后，将第二封装材料填充到切割槽中。因此，衬底单元的周边仍然被第二封装材料的残余物封装在单独处理之后，其中衬底单元被分割成单独的半导体封装以防止衬底单元的周边暴露。

5. 发明授权

US08093104B1 Multi-chip stacking method to reduce voids between stacked chips 有权
标题翻译：多芯片堆叠方法，以减少堆叠芯片之间的空隙
公开(公告)号：US08093104B1
公开(公告)日：2012-01-10
申请号：US13042136
申请日：2011-03-07
申请人： Kuo-Yuan Lee , Yung-Hsiang Chen , Wen-Chun Chiu
发明人： Kuo-Yuan Lee , Yung-Hsiang Chen , Wen-Chun Chiu
IPC分类号： H01L21/00
CPC分类号： H01L23/3128 , H01L21/561 , H01L21/565 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48227 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/85423 , H01L2224/85447 , H01L2224/8592 , H01L2224/97 , H01L2225/0651 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01059 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2224/92247 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2924/00014
摘要： A multi-chip stacking method to reduce voids between stacked chips is revealed. A first chip is disposed on a substrate, and a plurality of first bonding wires are formed by wire bonding to electrically connect the first chip and the substrate. A second chip is disposed on an active surface of the first chip where a dielectric layer and a FOW adhesive (film over wire) adhesive are attached onto a back surface of the second chip. The FOW adhesive partially encapsulates the first bonding wires and adheres to the active surface of the first chip. Then, the substrate is placed in a pressure oven to provide a positive pressure greater than one atm during thermally curing the FOW adhesive with exerted pressures. Accordingly, voids can be reduced inside the FOW adhesive during the multi-chip stacked processes where issues of poor adhesion and popcorn between chips can be avoided.
摘要翻译：揭示了减少堆叠芯片之间的空隙的多芯片堆叠方法。第一芯片设置在基板上，并且通过引线接合形成多个第一接合线以电连接第一芯片和基板。第二芯片设置在第一芯片的有源表面上，其中电介质层和FOW粘合剂（膜上电缆）粘合剂附着到第二芯片的背表面上。 FOW粘合剂部分地封装第一粘合线并粘附到第一芯片的有效表面。然后，在施加压力的FOW粘合剂热固化期间，将基底放置在压力烘箱中以提供大于1atm的正压。因此，在多芯片堆叠过程中，可以在FOW粘合剂内部减少空隙，其中可以避免芯片之间的粘附不良和爆米花的问题。

6. 发明授权

US08815645B2 Multi-chip stacking method to reduce voids between stacked chips 有权
标题翻译：多芯片堆叠方法，以减少堆叠芯片之间的空隙
公开(公告)号：US08815645B2
公开(公告)日：2014-08-26
申请号：US13311257
申请日：2011-12-05
申请人： Kuo-Yuan Lee , Yung-Hsiang Chen , Wen-Chun Chiu
发明人： Kuo-Yuan Lee , Yung-Hsiang Chen , Wen-Chun Chiu
IPC分类号： H01L21/00 , H01L25/065 , H01L23/00 , H01L21/56 , H01L25/00 , H01L23/31
CPC分类号： H01L21/565 , H01L21/561 , H01L23/3128 , H01L24/04 , H01L24/06 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/04042 , H01L2224/05554 , H01L2224/06135 , H01L2224/06136 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48479 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/83191 , H01L2224/838 , H01L2224/85013 , H01L2224/85186 , H01L2224/8592 , H01L2224/85951 , H01L2224/97 , H01L2225/0651 , H01L2225/06565 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01059 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2224/92247 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/4554 , H01L2224/85399 , H01L2224/05599
摘要： A multi-chip stacking method to reduce voids between stacked chips is revealed. A first chip is disposed on a substrate, and a plurality of first bonding wires are formed by wire bonding to electrically connect the first chip and the substrate. A second chip is disposed on an active surface of the first chip where a FOW (film over wire) adhesive is formed on a back surface of the second chip. The FOW adhesive partially encapsulates the first bonding wires and adheres to the active surface of the first chip. Then, the substrate is placed in a pressure oven to provide a positive pressure greater than one atm during thermally curing the FOW adhesive with exerted pressures. Accordingly, voids can be reduced inside the FOW adhesive during the multi-chip stacked processes where issues of poor adhesion and popcorn between chips can be avoided.
摘要翻译：揭示了减少堆叠芯片之间的空隙的多芯片堆叠方法。第一芯片设置在基板上，并且通过引线接合形成多个第一接合线以电连接第一芯片和基板。第二芯片设置在第一芯片的有源表面上，其中在第二芯片的背面上形成有FOW（覆膜上）粘合剂。 FOW粘合剂部分地封装第一粘合线并粘附到第一芯片的有效表面。然后，在施加压力的FOW粘合剂热固化期间，将基底放置在压力烘箱中以提供大于1atm的正压。因此，在多芯片堆叠过程中，可以在FOW粘合剂内部减少空隙，其中可以避免芯片之间的粘附不良和爆米花的问题。

7. 发明申请

US20090166891A1 Cutting and molding in small windows to fabricate semiconductor packages 有权
标题翻译：在小窗户中切割和成型制造半导体封装
公开(公告)号：US20090166891A1
公开(公告)日：2009-07-02
申请号：US12003634
申请日：2007-12-28
申请人： Kuo-Yuan Lee , Yung-Hsiang Chen
发明人： Kuo-Yuan Lee , Yung-Hsiang Chen
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L21/561 , H01L23/3128 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/49 , H01L2224/73215 , H01L2224/92 , H01L2224/92147 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A method for cutting and molding in small windows of a window-type semiconductor package and the semiconductor package fabricated from the same are revealed. According to the method, a substrate strip has a plurality of small windows disposed at the sides or at the corners of the substrate strip. The external surface of the substrate strip includes a plurality of window molding areas surrounding the small windows and extending to the scribe lines. A plurality of chips are disposed on the substrate strip. Then, an encapsulant is formed in the small windows to encapsulate the electrical connecting components and formed on the window molding areas so that the encapsulant extends to the scribe lines. Therefore, the mold flashes at the small windows can be effectively reduced. Additionally, the encapsulnat on the window molding areas is cut when singulating the substrate units so that the adhesion area of the encapsulant to the substrate strip is increased to prevent the delamination of traces and solder mask of the substrate units.
摘要翻译：揭示了一种在窗型半导体封装的小窗口中切割和模制的方法以及由其制造的半导体封装。根据该方法，衬底条具有设置在衬底条的侧面或拐角处的多个小窗口。衬底条的外表面包括围绕小窗口并延伸到划线的多个窗口模制区域。多个芯片设置在基板条上。然后，在小窗口中形成密封剂以封装电连接部件并形成在窗口成型区域上，使得密封剂延伸到划线。因此，模具在小窗口闪烁可以有效降低。此外，当单个衬底单元时，在窗口成型区域上的密封件被切割，使得密封剂与衬底带的粘合面积增加以防止衬底单元的迹线和焊接掩模的分层。

8. 发明申请

US20090134504A1 Semiconductor package and packaging method for balancing top and bottom mold flows from window 审中-公开
标题翻译：半导体封装和封装方法，用于平衡来自窗户的顶部和底部模具流
公开(公告)号：US20090134504A1
公开(公告)日：2009-05-28
申请号：US11987229
申请日：2007-11-28
申请人： Kuo-Yuan Lee , Yung-Hsiang Chen
发明人： Kuo-Yuan Lee , Yung-Hsiang Chen
IPC分类号： H01L23/13 , H01L21/56
CPC分类号： H01L23/4951 , H01L21/565 , H01L23/13 , H01L23/3128 , H01L24/06 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/48247 , H01L2224/73215 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A window-type semiconductor package to balance top and bottom moldflows and its method are revealed. The package primarily comprises a substrate having a slot, a chip, and an encapsulant. After die attaching, an input opening and an output opening are formed and exposed from both ends of the slot. The slot is off-center designed so that the dimension of the input opening is smaller than the one of the output opening. The encapsulant has a top molding portion formed on the top surface of the substrate and a smaller bottom molding portion formed on the bottom surface of the substrate. The mold-flowing speeds between the top molding portion and the bottom molding portion are balanced to eliminate trapped air bubbles in the top mold and to avoid the flooding of the molding compound in the bottom mold.
摘要翻译：揭示了一种用于平衡顶部和底部模具流的窗式半导体封装及其方法。该封装主要包括具有狭缝，芯片和密封剂的衬底。裸片安装后，从槽的两端形成并露出输入开口和输出开口。插槽偏心设计，使得输入开口的尺寸小于输出开口的尺寸。密封剂具有形成在基材的顶表面上的顶部模塑部分和形成在基材的底表面上的较小的底部模制部分。顶部成型部分和底部成型部分之间的模具流动速度是平衡的，以消除顶部模具中的被捕获的气泡并且避免模制化合物在底部模具中的溢流。

9. 发明申请

US20090294792A1 CARD TYPE MEMORY PACKAGE 审中-公开
标题翻译：卡类型存储包
公开(公告)号：US20090294792A1
公开(公告)日：2009-12-03
申请号：US12130518
申请日：2008-05-30
申请人： Kuo-Yuan Lee , Ke-Wen Lu , Ta-Wei Kuo , Wen-Chun Chiu , Pi-Wei Hsu
发明人： Kuo-Yuan Lee , Ke-Wen Lu , Ta-Wei Kuo , Wen-Chun Chiu , Pi-Wei Hsu
IPC分类号： H01L33/00
CPC分类号： G06K19/07745 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2225/0651 , H01L2924/00014 , H01L2924/01079 , H01L2924/07802 , H01L2924/12041 , H01L2924/181 , H01L2924/1815 , H01L2924/19105 , H01L2924/0002 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A card-type memory package is revealed, primarily comprising a substrate, a plurality of gold fingers, at least a memory chip, an LED chip, and an encapsulant. The memory chip and the LED chip are disposed on an encapsulated surface of the substrate with the LED chip adjacent to a rear side of the substrate. The gold fingers are attached to the substrate adjacent to a front side of the substrate. The encapsulant is formed on the encapsulated surface to encapsulate the memory chip and the LED chip with the gold fingers exposed. Therefore, the card-type memory package has the LED indication of reading and writing information with simplified assembling processes.
摘要翻译：显示了一种卡型存储器封装，主要包括基板，多个金指，至少存储芯片，LED芯片和密封剂。存储芯片和LED芯片设置在衬底的封装表面上，其中LED芯片与衬底的后侧相邻。金指与衬底的前侧相邻地附接到衬底。密封剂形成在封装的表面上，以封住存储芯片和带有金指的LED芯片。因此，卡式存储器包具有读取和写入信息的LED指示，具有简化的组装过程。

10. 发明申请

US20130266923A1 Interactive Multimedia Instructional System and Device 审中-公开
标题翻译：交互式多媒体教学系统与设备
公开(公告)号：US20130266923A1
公开(公告)日：2013-10-10
申请号：US13442872
申请日：2012-04-10
申请人： Kuo-Yuan Lee
发明人： Kuo-Yuan Lee
IPC分类号： G09B5/00
CPC分类号： G09B5/08
摘要： An interactive multimedia instructional system and device include a wireless guidance unit used by an instructor and plural wireless interaction units used by pupils. The wireless guidance unit and the wireless interaction units are connected wirelessly with a computer host loaded with a multisite and point-and-click operating system and instructional software. A display unit is connected with the computer host to display execution pictures of the instructional software and to display pointers by the wireless guidance unit and the wireless interaction units. The instructional software includes a group management program and a lesson plan editing interface on the display unit. As a result, one-to-many interactive multimedia teaching that is more enriched, vivid and effective can be achieved through this electronic instructional system, between the instructor and the pupils.
摘要翻译：交互式多媒体教学系统和装置包括由导师使用的无线引导单元和学生使用的多个无线互动单元。无线引导单元和无线交互单元与装载有多站点和点击操作系统和教学软件的计算机主机无线连接。显示单元与计算机主机连接以显示指导软件的执行画面，并通过无线引导单元和无线交互单元显示指针。教学软件在显示单元上包括组管理程序和课程计划编辑界面。因此，通过电子教学系统，教师和学生之间的一对多互动多媒体教学，可以更加丰富，生动有效地实现。

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