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1. 发明授权

US06185674B2 Method and apparatus for reconstructing the address of the next instruction to be completed in a pipelined processor 失效
标题翻译：用于重构在流水线处理器中要完成的下一条指令的地址的方法和装置
公开(公告)号：US06185674B2
公开(公告)日：2001-02-06
申请号：US08417421
申请日：1995-04-05
申请人： Kin Shing Chan , Chiao-Mei Chuang , Alessandro Marchioro
发明人： Kin Shing Chan , Chiao-Mei Chuang , Alessandro Marchioro
IPC分类号： G06F900
CPC分类号： G06F9/322
摘要： A computer processing unit is provided that includes an apparatus for generating an address of the next instruction to be completed. The apparatus includes a first table for storing a plurality of entries each corresponding to a dispatched instruction, each entry comprising an identifier that identifies the corresponding instruction and a status bit that indicates if the corresponding instruction is completed; a second table for storing a plurality of entries each corresponding to dispatched branch instructions, each entry comprising the same identifier stored in the first table, a target address of the dispatched branch instruction and a resolution status field that indicates at least if the corresponding branch instruction has been resolved taken or has been resolved not taken; program counter update logic that, in each machine cycle, updates a program counter to store and output the address of the next instruction to be completed according to the entries stored in the first table and the second table. Because the first and second tables employ efficient identification tags to identify instructions that modify the control flow of the execution pipeline and the target address of such instructions, the computer processing unit of the present invention need not store the full address of each instruction in the execution pipeline to update the program counter as is conventional, and thus saves real estate that may be used for other circuitry.
摘要翻译：提供一种计算机处理单元，其包括用于生成要完成的下一条指令的地址的装置。该装置包括：第一表，用于存储与分派指令对应的多个条目;每个条目包括识别对应指令的标识符和指示相应指令是否完成的状态位; 用于存储多个条目的第二表，每个条目各自对应于分派的分支指令，每个条目包括存储在第一表中的相同标识符，分派的分支指令的目标地址和分辨率状态字段，其至少指示相应的分支指令已解决或已解决不采取; 程序计数器更新逻辑，其在每个机器周期中根据存储在第一表和第二表中的条目更新程序计数器以存储和输出要完成的下一个指令的地址。因为第一和第二表使用有效用于识别修改执行流水线的控制流程和这些指令的目标地址的指令的识别标签，本发明的计算机处理单元不需要在执行流水线中存储每条指令的完整地址以更新程序计数器并且因此节省可用于其它电路的不动产。

2. 发明授权

US5777918A Fast multiple operands adder/subtracter based on shifting 失效
标题翻译：基于移位的快速多操作数加法器/减法器
公开(公告)号：US5777918A
公开(公告)日：1998-07-07
申请号：US600691
申请日：1996-02-13
申请人： Kin Shing Chan , Chiao-Mei Chuang , Sang Hoo Dhong , Alessandro Marchioro
发明人： Kin Shing Chan , Chiao-Mei Chuang , Sang Hoo Dhong , Alessandro Marchioro
IPC分类号： G06F7/50 , G06F7/509
CPC分类号： G06F7/509 , G06F7/5057 , G06F7/4991
摘要： A fast adder/subtracter using a decoder and shifting function instead of conventional full-adders is disclosed. The circuit is optimized for the addition of multiple operands up to 4-5 binary bits in magnitude. Using this method a subtraction operation can be performed at no added cost with respect to addition (compared to the conventional method requiring complementing one of the operands). Addition and subtraction of multiple operands is implemented by simple multiple shift operations. The multiple shift operations can be implemented as a chain of series NMOS pulldown devices with a precharged load providing considerable speed advantage over conventional solutions. Fast overflow detection may be implemented by or-ing the higher order bits in the shifter.
摘要翻译：公开了一种使用解码器和移位功能而不是传统的全加器的快速加法器/减法器。该电路经过优化，可增加多达4-5个二进制位的操作数。使用该方法，相对于添加，可以不添加成本来执行减法运算（与需要补充操作数之一的常规方法相比）。通过简单的多重移位操作来实现多个操作数的加减。多个移位操作可以被实现为具有预充电负载的串联NMOS下拉器件链，其提供相对于常规解决方案相当大的速度优势。快速溢出检测可以通过移位器中的较高位实现。

3. 发明授权

US5502683A Dual ported memory with word line access control 失效
标题翻译：双端口存储器，具有字线访问控制
公开(公告)号：US5502683A
公开(公告)日：1996-03-26
申请号：US49921
申请日：1993-04-20
申请人： Alessandro Marchioro
发明人： Alessandro Marchioro
IPC分类号： G06F12/06 , G06F12/08 , G11C8/16 , G11C11/41 , G11C8/00
CPC分类号： G06F12/0853 , G11C8/16 , G06F12/0886
摘要： In order to access several pieces of information concurrently, computers can make use of multi-port access memories. This invention introduces a circuit for a memory system that can be used in such applications. Dual-ported memory access is achieved without duplication of the memory arrays or of the word and bit lines used in the circuit. The circuit allows concurrent read and/or write operations by controlling access to independently controlled sections of the word lines in a memory array and is useful for dual ported data caches. In instruction cache memory applications, the circuitry can be used to allow concurrent access to a number of multiple words. The total number of words accessed concurrently is equal to the total cache width and is independent of the address of the lowest word being accessed.
摘要翻译：为了同时访问几个信息，计算机可以利用多端口访问存储器。本发明引入了可用于这种应用的存储器系统的电路。实现双端口存储器访问，而不会重复存储器阵列或电路中使用的字和位线。该电路通过控制对存储器阵列中字线的独立控制部分的访问来允许并行读取和/或写入操作，并且对于双端口数据高速缓存是有用的。在指令高速缓存存储器应用中，电路可用于允许并发访问多个多个字。同时访问的总字数等于总缓存宽度，并且与被访问的最低字的地址无关。

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