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1. 发明申请

US20110253428A1 CIRCUIT BOARD WITH NOTCHED STIFFENER FRAME 有权
标题翻译：电路板带有加强型框架
公开(公告)号：US20110253428A1
公开(公告)日：2011-10-20
申请号：US12759761
申请日：2010-04-14
申请人： Kevin W. Lim , Seah S. Too , Mohammad Z. Khan
发明人： Kevin W. Lim , Seah S. Too , Mohammad Z. Khan
IPC分类号： H05K1/02 , H01R43/00 , H05K1/18
CPC分类号： H01L23/16 , H01L21/563 , H01L24/16 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0655 , H01L25/0657 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81815 , H01L2224/83007 , H01L2224/83102 , H01L2224/83385 , H01L2224/92125 , H01L2924/01029 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/3511 , H05K1/181 , H05K2201/0272 , H05K2201/10674 , H05K2201/2018 , Y10T29/49117 , H01L2924/00
摘要： Various embodiments of a semiconductor chip device that include a circuit board and a stiffener frame and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a circuit board and coupling a stiffener frame to the circuit board. The stiffener frame includes a first opening that defines an interior wall. The interior wall includes a notch.
摘要翻译：公开了包括电路板和加强筋框架的半导体芯片器件的各种实施例及其制造方法。一方面，提供一种制造方法，其包括提供电路板并将加强框架耦合到电路板。加强框架包括限定内壁的第一开口。内墙包括一个凹口。

2. 发明授权

US08232138B2 Circuit board with notched stiffener frame 有权
标题翻译：电路板带缺口加强框架
公开(公告)号：US08232138B2
公开(公告)日：2012-07-31
申请号：US12759761
申请日：2010-04-14
申请人： Kevin W. Lim , Seah S. Too , Mohammad Z. Khan
发明人： Kevin W. Lim , Seah S. Too , Mohammad Z. Khan
IPC分类号： H01L21/00 , H01L23/48
CPC分类号： H01L23/16 , H01L21/563 , H01L24/16 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0655 , H01L25/0657 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81815 , H01L2224/83007 , H01L2224/83102 , H01L2224/83385 , H01L2224/92125 , H01L2924/01029 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/3511 , H05K1/181 , H05K2201/0272 , H05K2201/10674 , H05K2201/2018 , Y10T29/49117 , H01L2924/00
摘要： Various embodiments of a semiconductor chip device that include a circuit board and a stiffener frame and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a circuit board and coupling a stiffener frame to the circuit board. The stiffener frame includes a first opening that defines an interior wall. The interior wall includes a notch.
摘要翻译：公开了包括电路板和加强框架的半导体芯片器件的各种实施例及其制造方法。一方面，提供一种制造方法，其包括提供电路板并将加强框架耦合到电路板。加强框架包括限定内壁的第一开口。内墙包括一个凹口。

3. 发明授权

US06409070B1 Minimizing flux residue by controlling amount of moisture during reflow 有权
标题翻译：通过控制回流期间的水分量来最大限度地减少助焊剂残留量
公开(公告)号：US06409070B1
公开(公告)日：2002-06-25
申请号：US09663939
申请日：2000-09-18
申请人： Raj N. Master , Mohammad Z. Khan , Maria G. Guardado , Diong Hing Ding , Junaida Abu Bakar
发明人： Raj N. Master , Mohammad Z. Khan , Maria G. Guardado , Diong Hing Ding , Junaida Abu Bakar
IPC分类号： B23K3102
CPC分类号： B23K1/203 , B23K2101/40 , H01L2224/16225 , H01L2224/73204 , H05K3/3436 , H05K3/3489
摘要： A method of manufacturing a flip-chip semiconductor device by attaching a semiconductor die to a substrate using solder comprises the steps of applying a no-clean flux to the semiconductor die and the substrate; heating the solder and the flux in a furnace to bond the semiconductor die to the substrate; and underfilling between the semiconductor die and the substrate. While the solder and flux is being heated, a reducing atmosphere in the furnace is being measured to determine the moisture content. When the moisture content exceeds a threshold amount, a signal will be provided. A reflow furnace for practicing the method is also disclosed.
摘要翻译：通过使用焊料将半导体管芯附着到衬底来制造倒装芯片半导体器件的方法包括以下步骤：向半导体管芯和衬底施加免清洗助焊剂; 在炉中加热焊料和焊剂以将半导体管芯粘合到衬底上; 并且在半导体管芯和衬底之间的底部填充。当焊料和焊剂被加热时，测量炉中的还原气氛以确定含水量。当水分含量超过阈值时，将提供信号。还公开了用于实施该方法的回流炉。

4. 发明授权

US06371310B1 Boat for land grid array packages 失效
标题翻译：船用地电网阵列包
公开(公告)号：US06371310B1
公开(公告)日：2002-04-16
申请号：US09740838
申请日：2000-12-21
申请人： Raj N. Master , Mohammad Z. Khan , L. K. Teoh
发明人： Raj N. Master , Mohammad Z. Khan , L. K. Teoh
IPC分类号： A47F700
CPC分类号： H01L21/67333
摘要： A boat is formed with layers comprising substantially aligned holes for safely accommodating land grid array semiconductor packages during assembly. The boat includes a bottom layer with an array of through-holes having a substantially square cross-sectional shape with rounded corners, a middle layer with an array of through-holes having a substantially octagonal cross-sectional shape and a top layer having an array of through-holes having a substantially square cross-sectional shape with notched sides and vertical tabs extending upwardly from the sidewalls of each notched side. The layers may be attached by spot welding or other means.
摘要翻译：船形成有包括基本上对准的孔的层，用于在组装期间安全地容纳平台阵列半导体封装。船包括具有基本上具有圆角的基本正方形横截面形状的通孔阵列的底层，具有基本上八边形横截面形状的通孔阵列的中间层和具有阵列的顶层的通孔具有基本正方形的横截面形状，具有切口侧面和从每个缺口侧的侧壁向上延伸的垂直突出部。这些层可以通过点焊或其他方式附着。

5. 发明授权

US5988485A Flux cleaning for flip chip technology using environmentally friendly solvents 失效
标题翻译：使用环保溶剂的倒装芯片技术的助焊剂清洗
公开(公告)号：US5988485A
公开(公告)日：1999-11-23
申请号：US40651
申请日：1998-03-17
申请人： Raj N. Master , Orion K. Starr , Mohammad Z. Khan
发明人： Raj N. Master , Orion K. Starr , Mohammad Z. Khan
IPC分类号： H01L21/60 , H01L21/48 , B23K1/018
CPC分类号： H01L21/4864 , H01L2224/83192 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701
摘要： A method of assembling a substrate and die in a flip chip configuration uses a non-hazardous cleaning solvent to clean the flux residue. The non-hazardous cleaning solvent utilized is Ionox obtained from Kyzen Corporation. Optimized process parameters are: time 10-30 minutes, temperature 70-90.degree. C., pressure 40-70 psi, rotation speed and reversals 100-1000 rpm and 24-100 reversal cycles.
摘要翻译：以倒装芯片配置组装衬底和管芯的方法使用非危险清洁溶剂来清洁焊剂残留物。使用的非危险清洗溶剂是从Kyzen Corporation获得的Ionox。优化的工艺参数为：时间10-30分钟，温度70-90℃，压力40-70psi，转速和反转100-1000转和24-100反转循环。

6. 发明授权

US06722553B2 Controlled and programmed deposition of flux on a flip-chip die by spraying 失效
标题翻译：通过喷涂控制并编程在倒装芯片上沉积助焊剂
公开(公告)号：US06722553B2
公开(公告)日：2004-04-20
申请号：US09922936
申请日：2001-08-07
申请人： Raj N. Master , Mohammad Z. Khan , Maria G. Guardado , Ooi Tong Ong
发明人： Raj N. Master , Mohammad Z. Khan , Maria G. Guardado , Ooi Tong Ong
IPC分类号： B23K1308
CPC分类号： H05K3/3489 , B23K1/203 , B23K2101/36 , H05K3/3436
摘要： A method and apparatus are provided for controllably dispensing flux on a substrate having a plurality of conductive terminals. Flux having a viscosity range between 10 centipoises and about 150 centipoises is sprayed on the substrate and the conductive terminals at a valve pressure range between about 1.5 psi and about 30 psi via a dispense nozzle of a flux dispenser. Upon a subsequent high temperature solder reflow process, the sprayed flux on the substrate is mostly removed by thermal decomposition to volatile species, thereby significantly reducing flux residue remaining on the surface of the substrate between the conductive terminals.
摘要翻译：提供了一种方法和装置，用于在具有多个导电端子的基板上可控地分配通量。具有10厘泊和约150厘泊之间的粘度范围的助焊剂通过焊剂分配器的分配喷嘴在约1.5psi至约30psi之间的阀压力范围内喷射到衬底和导电端子上。在随后的高温焊料回流工艺中，基板上的喷涂焊剂主要通过热分解除去到挥发性物质，从而显着减少在导电端子之间残留在基板表面上的焊剂残余物。

7. 发明授权

US06617195B1 Method of reflowing organic packages using no-clean flux 有权
标题翻译：使用无清洁助焊剂回流有机包装的方法
公开(公告)号：US06617195B1
公开(公告)日：2003-09-09
申请号：US09624491
申请日：2000-07-24
申请人： Raj N. Master , Mohammad Z. Khan , Maria G. Guardado
发明人： Raj N. Master , Mohammad Z. Khan , Maria G. Guardado
IPC分类号： H01L2144
CPC分类号： H01L24/81 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01075 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H05K3/3494
摘要： A method of manufacturing a semiconductor device by attaching a flip chip die to an organic substrate using solder comprises applying no-clean flux to the flip chip die or the organic substrate; heating the flip chip die and the organic substrate to bond the flip chip die to the organic substrate, and cooling the flip chip die and the organic substrate. The step of heating the flux includes controlling oxygen and moisture content of an atmosphere surrounding the flux, preheating to a temperature of about 145° C. to about 165° C., soaking at a temperature of about 145° C. to about 165° C. for about four to about six minutes, and reflowing above the solder's melting point.
摘要翻译：通过使用焊料将倒装芯片裸片附着到有机基板来制造半导体器件的方法包括向倒装芯片或有机基板施加免清洗助焊剂; 加热倒装晶片管芯和有机衬底以将倒装晶片管芯结合到有机衬底上，并冷却倒装晶片管芯和有机衬底。加热焊剂的步骤包括控制焊剂周围的气氛中的氧气和水分含量，预热至约145℃至约165℃的温度，在约145℃至约165℃的温度下浸泡 C.约4至6分钟，并回流焊料熔点以上。

8. 发明授权

US5572692A Memory configuration decoding system having automatic row base address generation mechanism for variable memory devices with row access interleaving 失效
标题翻译：存储器配置解码系统，具有用于具有行访问交错的可变存储器设备的自动行基地址生成机制
公开(公告)号：US5572692A
公开(公告)日：1996-11-05
申请号：US143984
申请日：1993-10-27
申请人： Robert N. Murdoch , Mohammad Z. Khan
发明人： Robert N. Murdoch , Mohammad Z. Khan
IPC分类号： G06F12/02 , G11C8/00 , G11C8/12 , G06F12/06
CPC分类号： G11C8/00 , G06F12/0292 , G11C8/12
摘要： A memory configuration system including a memory controller comprising a set of memory configuration registers which store information related to memory devices installed in random access memory. The memory configuration registers correspond to one or more rows of memory banks in the random access memory. The memory controller also includes a row size and mask generator coupled to the memory configuration register set and a memory configuration decoder coupled to the row size and mask generator. The combination of logic within the row size and mask generator and the memory configuration decoder is used to generate a base address for each row of memory locations within the random access memory. The present invention automatically reconfigures the memory array to define the most populous row as Row 0 regardless of where the largest row is physically populated. This reconfiguration of the memory array is the logical to physical mapping feature provided by the present invention. As an additional feature, the present invention provides a default memory configuration means (i.e. default ordering of rows) for performing the logical to physical mapping in a predictable manner when two or more rows are populated with equal amounts of memory.
摘要翻译：一种存储器配置系统，包括存储器控制器，该存储器控制器包括一组存储器配置寄存器，其存储与安装在随机存取存储器中的存储器件有关的信息存储器配置寄存器对应于随机存取存储器中的一行或多行存储体。存储器控制器还包括耦合到存储器配置寄存器组的行大小和掩码生成器以及耦合到行大小和掩码生成器的存储器配置解码器。行大小和掩码生成器和存储器配置解码器之间的逻辑的组合用于为随机存取存储器内的每行存储单元生成基地址。本发明自动重新配置存储器阵列以将最大容量的行定义为行0，而不管最大行在物理上的填充位置。存储器阵列的这种重新配置是本发明提供的逻辑到物理映射特征。作为附加特征，本发明提供了一种默认存储器配置装置（即，行的默认顺序），用于当以相等量的存储器填充两行或多行时，以可预测的方式执行逻辑到物理映射。

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