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1. 发明申请

US20050030949A1 Fast and adaptive packet processing device and method using digest information of input packet 审中-公开
公开(公告)号：US20050030949A1
公开(公告)日：2005-02-10
申请号：US10934460
申请日：2004-09-07
申请人： Kenji Shirakawa , Yasuro Shobatake , Toshio Okamoto , Yoshimitsu Shimojo
发明人： Kenji Shirakawa , Yasuro Shobatake , Toshio Okamoto , Yoshimitsu Shimojo
IPC分类号： G06F9/22 , G06F9/28 , G06F15/16 , H04L12/70 , H04L29/06 , H04L12/28
CPC分类号： H04L45/00 , H04L29/06 , H04L45/566 , H04L69/22
摘要： A packet processing device is formed by a digest information generation unit configured to extract a plurality of prescribed bit sequences from an input packet, and generate a digest information capable of specifying at least a part of a processing to be applied to the input packet, according to values of the plurality of prescribed bit sequences; and a packet processing unit configured to process the input packet using an instruction sequence to be applied to the input packet that is obtained according to the digest information generated by the digest information generation unit, where the digest information generation unit generates the digest information with respect to a next input packet while the packet processing unit carries out a processing for one packet.

2. 发明授权

US07027442B2 Fast and adaptive packet processing device and method using digest information of input packet 失效
标题翻译：快速自适应分组处理设备和方法，使用输入分组的摘要信息
公开(公告)号：US07027442B2
公开(公告)日：2006-04-11
申请号：US10934440
申请日：2004-09-07
申请人： Kenji Shirakawa , Yasuro Shobatake , Toshio Okamoto , Yoshimitsu Shimojo
发明人： Kenji Shirakawa , Yasuro Shobatake , Toshio Okamoto , Yoshimitsu Shimojo
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , H04L29/06 , H04L45/566 , H04L69/22
摘要： A packet processing device is formed by a digest information generation unit configured to extract a plurality of prescribed bit sequences from an input packet, and generate a digest information capable of specifying at least a part of a processing to be applied to the input packet, according to values of the plurality of prescribed bit sequences; and a packet processing unit configured to process the input packet using an instruction sequence to be applied to the input packet that is obtained according to the digest information generated by the digest information generation unit, where the digest information generation unit generates the digest information with respect to a next input packet while the packet processing unit carries out a processing for one packet.
摘要翻译：分组处理设备由摘要信息生成单元形成，该摘要信息生成单元被配置为从输入分组提取多个规定的比特序列，并且生成能够指定要应用于输入分组的处理的至少一部分的摘要信息，根据到所述多个规定位序列的值; 以及分组处理单元，被配置为使用将要应用于根据由摘要信息生成单元生成的摘要信息获得的输入分组的指示序列来处理输入分组，其中摘要信息生成单元生成相关的摘要信息到分组处理单元对一个分组进行处理的下一个输入分组。

3. 发明申请

US20050086353A1 Fast and adaptive packet processing device and method using digest information of input packet 失效
标题翻译：快速自适应分组处理设备和方法，使用输入分组的摘要信息
公开(公告)号：US20050086353A1
公开(公告)日：2005-04-21
申请号：US10934440
申请日：2004-09-07
申请人： Kenji Shirakawa , Yasuro Shobatake , Toshio Okamoto , Yoshimitsu Shimojo
发明人： Kenji Shirakawa , Yasuro Shobatake , Toshio Okamoto , Yoshimitsu Shimojo
IPC分类号： G06F9/22 , G06F9/28 , G06F15/16 , H04L12/70 , H04L29/06 , G06F15/00
CPC分类号： H04L45/00 , H04L29/06 , H04L45/566 , H04L69/22
摘要： A packet processing device is formed by a digest information generation unit configured to extract a plurality of prescribed bit sequences from an input packet, and generate a digest information capable of specifying at least a part of a processing to be applied to the input packet, according to values of the plurality of prescribed bit sequences; and a packet processing unit configured to process the input packet using an instruction sequence to be applied to the input packet that is obtained according to the digest information generated by the digest information generation unit, where the digest information generation unit generates the digest information with respect to a next input packet while the packet processing unit carries out a processing for one packet.
摘要翻译：分组处理设备由摘要信息生成单元形成，该摘要信息生成单元被配置为从输入分组提取多个规定的比特序列，并且生成能够指定要应用于输入分组的处理的至少一部分的摘要信息，根据到所述多个规定位序列的值; 以及分组处理单元，被配置为使用将要应用于根据由摘要信息生成单元生成的摘要信息获得的输入分组的指示序列来处理输入分组，其中摘要信息生成单元生成相关的摘要信息到分组处理单元对一个分组进行处理的下一个输入分组。

4. 发明授权

US06804240B1 Fast and adaptive packet processing device and method using digest information of input packet 失效
标题翻译：快速自适应分组处理设备和方法，使用输入分组的摘要信息
公开(公告)号：US06804240B1
公开(公告)日：2004-10-12
申请号：US09660459
申请日：2000-09-12
申请人： Kenji Shirakawa , Yasuro Shobatake , Toshio Okamoto , Yoshimitsu Shimojo
发明人： Kenji Shirakawa , Yasuro Shobatake , Toshio Okamoto , Yoshimitsu Shimojo
IPC分类号： H04L1256
CPC分类号： H04L45/00 , H04L29/06 , H04L45/566 , H04L69/22
摘要： A packet processing device is formed by a digest information generation unit configured to extract a plurality of prescribed bit sequences from an input packet, and generate a digest information capable of specifying at least a part of a processing to be applied to the input packet, according to values of the plurality of proscribed bit sequences; and a packet processing unit configured to process the input packet using an Instruction sequence to be applied to the input packet that is obtained according to the digest information generated by the digest information generation unit, where the digest information generation unit generates the digest information with respect to a next input packet while the packet processing unit carries out a processing for one packet.
摘要翻译：分组处理设备由摘要信息生成单元形成，该摘要信息生成单元被配置为从输入分组提取多个规定的比特序列，并且生成能够指定要应用于输入分组的处理的至少一部分的摘要信息，根据涉及多个被禁止的比特序列的值; 以及分组处理单元，被配置为使用要应用于根据由摘要信息生成单元生成的摘要信息获得的输入分组的指令序列来处理输入分组，其中摘要信息生成单元生成相关的摘要信息到分组处理单元对一个分组进行处理的下一个输入分组。

5. 发明授权

US5829041A Method and apparatus for managing single virtual space suitable for distributed processing 失效
标题翻译：用于管理适合分布式处理的单个虚拟空间的方法和装置
公开(公告)号：US5829041A
公开(公告)日：1998-10-27
申请号：US528335
申请日：1995-09-14
申请人： Toshio Okamoto , Tetsuro Kimura , Kenji Shirakawa
发明人： Toshio Okamoto , Tetsuro Kimura , Kenji Shirakawa
IPC分类号： G06F12/08 , G06F9/50 , G06F12/02 , G06F12/06 , G06F12/10 , G06F13/00
CPC分类号： G06F12/1072
摘要： A single virtual space management scheme suitable for a distributed system. The single virtual space for arranging programs and/or data among a plurality of computers forming the distributed system are divided into a plurality of regions called memory chapters, and a part of the single virtual space to be managed independently by each computer is requested from each computer in units of these memory chapters. Then, a server allocates one of the memory chapters to each computer in response to each request from each computer, while managing allocations of the memory chapters to the plurality of computers so as not to allocate each one of the memory chapters to more than one computers. Each memory chapter allocated to each computer is independently managed by further dividing each memory chapter into a plurality of sub-regions called memory sections, and carrying out an access protection in units of these memory sections at each computer.
摘要翻译：适用于分布式系统的单一虚拟空间管理方案。用于在形成分布式系统的多个计算机之间布置程序和/或数据的单个虚拟空间被划分为称为存储器章节的多个区域，并且从每个计算机请求由每台计算机独立管理的单个虚拟空间的一部分计算机以这些内存章为单位。然后，服务器响应于来自每个计算机的每个请求，向每个计算机分配其中一个内存章节，同时将多个存储器章节的分配管理到多个计算机，以便不将每个存储器章节分配给多个计算机。分配给每个计算机的每个存储器章节通过将每个存储器章节进一步划分成被称为存储器部分的多个子区域来独立地管理，并且在每个计算机处以这些存储器部分为单位执行访问保护。

6. 发明授权

US07353404B2 Tamper resistant microprocessor 失效
标题翻译：防篡改微处理器
公开(公告)号：US07353404B2
公开(公告)日：2008-04-01
申请号：US11071327
申请日：2005-03-04
申请人： Mikio Hashimoto , Keiichi Teramoto , Takeshi Saito , Kenji Shirakawa , Kensaku Fujimoto
发明人： Mikio Hashimoto , Keiichi Teramoto , Takeshi Saito , Kenji Shirakawa , Kensaku Fujimoto
IPC分类号： G06F21/00
CPC分类号： G06F21/10 , G06F21/123 , G06F21/72 , G06F2221/0797
摘要： Under a multi-task environment, a tamper resistant microprocessor saves a context information for one program whose execution is to be interrupted, where the context information contains information indicating an execution state of that one program and the execution code encryption key of that one program. An execution of that one program can be restarted by recovering the execution state of that one program from the saved context information. The context information can be encrypted by using the public key of the microprocessor, and then decrypted by using the secret key of the microprocessor.
摘要翻译：在多任务环境中，防篡改微处理器为执行中断的一个程序保存上下文信息，其中上下文信息包含指示该一个程序的执行状态的信息和该一个程序的执行代码加密密钥。可以通过从保存的上下文信息中恢复该一个程序的执行状态来重新启动该一个程序的执行。可以通过使用微处理器的公钥来加密上下文信息，然后使用微处理器的密钥进行解密。

7. 发明授权

US06287980B1 Plasma processing method and plasma processing apparatus 失效
标题翻译：等离子体处理方法和等离子体处理装置
公开(公告)号：US06287980B1
公开(公告)日：2001-09-11
申请号：US09415910
申请日：1999-10-12
申请人： Minoru Hanazaki , Takayuki Ikushima , Kenji Shirakawa , Shinji Yamaguchi , Masakazu Taki
发明人： Minoru Hanazaki , Takayuki Ikushima , Kenji Shirakawa , Shinji Yamaguchi , Masakazu Taki
IPC分类号： H01L2100
CPC分类号： H01L21/67069 , H01J37/3244
摘要： A plasma processing apparatus mainly comprises a processing chamber (10) formed by a vacuum vessel, a magnetic field forming coil (80) arranged around the processing chamber for forming a rotating magnetic field and gas supply means (101) supplying various gases to the processing chamber (10). The processing chamber (10) is divided into a reaction chamber (44) forming plasma with a partition wall (43) and a buffer chamber (45) discharging externally supplied gases with pressure difference. The reaction chamber (44) includes a high-frequency electrode arranged oppositely to the buffer chamber (45). The gas supply means (101) includes pulse gas valves (63a and 63b) for pulsatively supplying gases to the processing chamber (10). Thus provided are a plasma processing method and a plasma processing apparatus capable of uniformly processing a wafer having a large diameter and reducing RIE lag with respect to a fine etching pattern.
摘要翻译：一种等离子体处理装置主要包括由真空容器形成的处理室（10），设置在处理室周围的用于形成旋转磁场的磁场形成线圈（80），以及将各种气体供应至处理的气体供给装置室（10）。处理室（10）被分为形成等离子体的反应室（44）和分隔壁（43）以及缓冲室（45），该压力室排出外部供应压力差的气体。反应室（44）包括与缓冲室（45）相对布置的高频电极。气体供给装置（101）包括用于向处理室（10）脉动地供给气体的脉冲气体阀（63a和63b）。这样提供了一种等离子体处理方法和等离子体处理装置，其能够均匀地处理具有大直径的晶片并且相对于精细蚀刻图案减小RIE滞后。

8. 发明授权

US5269881A Plasma processing apparatus and plasma cleaning method 失效
标题翻译：等离子体处理装置和等离子体清洗方法
公开(公告)号：US5269881A
公开(公告)日：1993-12-14
申请号：US934828
申请日：1992-08-25
申请人： Hidenori Sekiya , Kenji Shirakawa
发明人： Hidenori Sekiya , Kenji Shirakawa
IPC分类号： C23C14/02 , B08B7/00 , C23C14/00 , C23C16/44 , C23G5/00 , H01J37/32 , H01L21/302 , H01L21/3065 , H01L21/306 , B44C1/22 , C23F1/00
CPC分类号： H01J37/32862 , B08B7/0035 , C23C16/4405 , C23G5/00 , H01J37/32082
摘要： There are disclosed apparatus and method for eliminating, by plasma cleaning, reaction products which are generated by etching and stick to an inner wall surface of a chamber. First to third conductive blocks (90a to 90c) are mounted on the inner wall surface of the chamber (50) through an insulator (92). A high-frequency electric field is applied sequentially between a first electrode (61) and the respective conductive blocks (90a to 90c) while a reactive gas is introduced into an internal space (51) of the chamber (50), to produce a plasma of the reactive gas. The reaction products which stick to the respective conductive blocks (90a to 90c) are sequentially gasified by the plasma of the reactive gas and exhausted to the outside of the chamber (50) to be eliminated.
摘要翻译：公开了通过等离子体清洗来消除通过蚀刻并粘附到室的内壁表面产生的反应产物的装置和方法。第一至第三导电块（90a至90c）通过绝缘体（92）安装在腔室（50）的内壁表面上。在第一电极（61）和各个导电块（90a〜90c）之间依次施加高频电场，同时将反应性气体引入到室（50）的内部空间（51）中，以产生等离子体的反应气体。粘附于各个导电块（90a〜90c）的反应产物依次被反应气体的等离子体气化并排出到室（50）的外部，以消除。

9. 发明授权

US07065215B2 Microprocessor with program and data protection function under multi-task environment 失效
公开(公告)号：US07065215B2
公开(公告)日：2006-06-20
申请号：US09984407
申请日：2001-10-30
申请人： Kenji Shirakawa , Mikio Hashimoto , Keiichi Teramoto , Satoshi Ozaki , Kensaku Fujimoto
发明人： Kenji Shirakawa , Mikio Hashimoto , Keiichi Teramoto , Satoshi Ozaki , Kensaku Fujimoto
IPC分类号： G06F17/00
CPC分类号： G06F21/71 , G06F2221/2105
摘要： In a microprocessor, a program key for decrypting a program and a data key for encrypting/decrypting data processed by the program are handled as cryptographically inseparable pair inside the microprocessor, so that it becomes possible for the microprocessor to protect processes that actually execute the program, without an intervention of the operating system, and it becomes possible to conceal secret information of the program not only from the other user program but also from the operating system.

10. 发明授权

US5236549A Process for plasma etching 失效
标题翻译：等离子体蚀刻过程
公开(公告)号：US5236549A
公开(公告)日：1993-08-17
申请号：US757364
申请日：1991-09-10
申请人： Kenji Shirakawa , Hidenori Sekiya
发明人： Kenji Shirakawa , Hidenori Sekiya
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3213
CPC分类号： H01L21/32136 , H01L21/32139
摘要： Plasma is produced continuously in an etching switching period for switching from a partial plasma etching process to the next partial plasma etching process to thereby proceed with anisotropic plasma etching even in the etching switching period. There is no period in which isotropic etching is performed throughout the process. The time period for executing the partial plasma etching process, which follows the etching switching period, is shortened while throughput is improved.
摘要翻译：在蚀刻切换期间连续地制造等离子体，用于从部分等离子体蚀刻工艺切换到下一部分等离子体蚀刻工艺，从而即使在蚀刻切换期间也进行各向异性等离子体蚀刻。在整个过程中不存在各向同性蚀刻的周期。用于执行蚀刻切换周期之后的部分等离子体蚀刻处理的时间段被缩短，同时提高了吞吐量。

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