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1. 发明申请

US20090149578A1 Block copolymer and method for producing same, composition for resin modification and modified resin composition, and method for producing same 有权
标题翻译：嵌段共聚物及其制造方法，树脂改性用组合物和改性树脂组合物及其制造方法
公开(公告)号：US20090149578A1
公开(公告)日：2009-06-11
申请号：US11989635
申请日：2006-07-27
申请人： Masao Nakamura , Kazuya Ito , Hidenori Yamagishi
发明人： Masao Nakamura , Kazuya Ito , Hidenori Yamagishi
IPC分类号： C08F2/60 , C08L47/00 , C08F136/20
CPC分类号： C08F297/02 , C08F287/00 , C08F297/04 , C08F297/044 , C08L51/006 , C08L53/02 , C08L2666/02
摘要： A comprising conjugated diene monomer units, and at least one polymer block B comprising conjugated diene monomer units and aromatic vinyl monomer units. This block copolymer is characterized in that (1) the polymer block A has a glass transition temperature of −88° C. to −45° C., (2) the polymer block B has a glass transition temperature of 30° C. to 90° C., (3) the content of aromatic vinyl monomer units in the whole block copolymer is 3-52 wt. %, (4) the aromatic vinyl block ratio in the whole block copolymer is smaller than 69 wt. %, and (5) the viscosity of a 5 wt. % solution of the block copolymer in styrene is 30-80 mPa·s. The block copolymer is useful as a resin modifier.
摘要翻译： A包含共轭二烯单体单元和至少一个包含共轭二烯单体单元和芳族乙烯基单体单元的聚合物嵌段B。该嵌段共聚物的特征在于，（1）聚合物嵌段A的玻璃化转变温度为-88℃〜-45℃，（2）聚合物嵌段B的玻璃化转变温度为30℃〜 90℃，（3）整个嵌段共聚物中芳族乙烯基单体单元的含量为3-52wt。％，（4）整个嵌段共聚物中的芳族乙烯基嵌段比小于69wt。％，和（5）5重量％的粘度。嵌段共聚物在苯乙烯中的％溶液为30-80mPa.s。嵌段共聚物可用作树脂改性剂。

2. 发明授权

US08637604B2 Block copolymer and method for producing same, composition for resin modification and modified resin composition, and method for producing same 有权
标题翻译：嵌段共聚物及其制造方法，树脂改性用组合物和改性树脂组合物及其制造方法
公开(公告)号：US08637604B2
公开(公告)日：2014-01-28
申请号：US11989635
申请日：2006-07-27
申请人： Masao Nakamura , Kazuya Ito , Hidenori Yamagishi
发明人： Masao Nakamura , Kazuya Ito , Hidenori Yamagishi
IPC分类号： C08F297/04 , C08L53/02 , C08L51/04
CPC分类号： C08F297/02 , C08F287/00 , C08F297/04 , C08F297/044 , C08L51/006 , C08L53/02 , C08L2666/02
摘要： A block copolymer comprising at least one polymer block A comprising conjugated diene monomer units, and at least one polymer block B comprising conjugated diene monomer units and aromatic vinyl monomer units. This block copolymer is characterized in that (1) the polymer block A has a glass transition temperature of −88° C. to −45° C., (2) the polymer block B has a glass transition temperature of 30° C. to 90° C., (3) the content of aromatic vinyl monomer units in the whole block copolymer is 3-52 wt. %, (4) the aromatic vinyl block ratio in the whole block copolymer is smaller than 69 wt. %, and (5) the viscosity of a 5 wt. % solution of the block copolymer in styrene is 30-80 mPa·s. The block copolymer is useful as a resin modifier.
摘要翻译：包含至少一种包含共轭二烯单体单元的聚合物嵌段A和至少一种包含共轭二烯单体单元和芳族乙烯基单体单元的聚合物嵌段B的嵌段共聚物。该嵌段共聚物的特征在于，（1）聚合物嵌段A的玻璃化转变温度为-88℃〜-45℃，（2）聚合物嵌段B的玻璃化转变温度为30℃〜 90℃，（3）整个嵌段共聚物中芳族乙烯基单体单元的含量为3-52wt。％，（4）整个嵌段共聚物中的芳族乙烯基嵌段比小于69wt。％，和（5）5重量％的粘度。嵌段共聚物在苯乙烯中的％溶液为30-80mPa·s。嵌段共聚物可用作树脂改性剂。

3. 发明授权

US08153727B2 Block copolymer, resin composition comprising same, and process for producing the resin composition 有权
标题翻译：嵌段共聚物，包含其的树脂组合物，以及树脂组合物的制造方法
公开(公告)号：US08153727B2
公开(公告)日：2012-04-10
申请号：US11920163
申请日：2006-05-08
申请人： Kazuya Ito , Hidenori Yamagishi , Masao Nakamura
发明人： Kazuya Ito , Hidenori Yamagishi , Masao Nakamura
IPC分类号： C08F297/04 , C08L53/02
CPC分类号： C08F297/04
摘要： A block copolymer comprised of a polymer block or blocks (A) comprising conjugated diene monomer units and a polymer block or blocks (B) comprising conjugated diene monomer units and aromatic vinyl monomer units, wherein (1) the polymer block or blocks (A) have a glass transition temperature in the range of −88 to −45° C., (2) the polymer block or blocks (B) have a glass transition temperature in the range of 30 to 90° C., (3) the content of aromatic vinyl monomer units in the block copolymer is in the range of 30 to 52% by weight based on the total weight of the block copolymer, (4) the block copolymer has an aromatic vinyl block ratio of smaller than 69% by weight based on the total weight of the block copolymer, and (5) the viscosity of a 5% by weight solution of the block copolymer in styrene is at least 5 mPa·s but smaller than 30 mPa·s. This block copolymer is used as a modifier for resin.
摘要翻译：由包含共轭二烯单体单元的聚合物嵌段或嵌段（A）和包含共轭二烯单体单元和芳族乙烯基单体单元的聚合物嵌段（B）组成的嵌段共聚物，其中（1）聚合物嵌段（A）玻璃化转变温度在-88〜-45℃的范围内，（2）聚合物嵌段（B）的玻璃化转变温度在30〜90℃的范围内，（3）含量嵌段共聚物中的芳香族乙烯基单体单元的含量相对于嵌段共聚物的总重量为30〜52重量％的范围，（4）嵌段共聚物的芳香族乙烯基嵌段比小于69重量％对于嵌段共聚物的总重量，（5）嵌段共聚物在苯乙烯中的5重量％溶液的粘度为至少5mPa·s，但小于30mPa·s。该嵌段共聚物用作树脂的改性剂。

4. 发明申请

US20090247700A1 Block copolymer, resin composition comprising same, and process for producing the resin composition 有权
标题翻译：嵌段共聚物，包含其的树脂组合物，以及树脂组合物的制造方法
公开(公告)号：US20090247700A1
公开(公告)日：2009-10-01
申请号：US11920163
申请日：2006-05-08
申请人： Kazuya Ito , Hidenori Yamagishi , Masao Nakamura
发明人： Kazuya Ito , Hidenori Yamagishi , Masao Nakamura
IPC分类号： C08L53/02 , C08L9/06
CPC分类号： C08F297/04
摘要： A block copolymer comprised of a polymer block or blocks (A) comprising conjugated diene monomer units and a polymer block or blocks (B) comprising conjugated diene monomer units and aromatic vinyl monomer units, wherein (1) the polymer block or blocks (A) have a glass transition temperature in the range of −88 to −45° C., (2) the polymer block or blocks (B) have a glass transition temperature in the range of 30 to 90° C., (3) the content of aromatic vinyl monomer units in the block copolymer is in the range of 30 to 52% by weight based on the total weight of the block copolymer, (4) the block copolymer has an aromatic vinyl block ratio of smaller than 69% by weight based on the total weight of the block copolymer, and (5) the viscosity of a 5% by weight solution of the block copolymer in styrene is at least 5 mPa·s but smaller than 30 mPa·s. This block copolymer is used as a modifier for resin.
摘要翻译：由包含共轭二烯单体单元的聚合物嵌段或嵌段（A）和包含共轭二烯单体单元和芳族乙烯基单体单元的聚合物嵌段（B）组成的嵌段共聚物，其中（1）聚合物嵌段（A）玻璃化转变温度在-88〜-45℃的范围内，（2）聚合物嵌段（B）的玻璃化转变温度在30〜90℃的范围内，（3）含量嵌段共聚物中的芳香族乙烯基单体单元的含量相对于嵌段共聚物的总重量为30〜52重量％的范围，（4）嵌段共聚物的芳香族乙烯基嵌段比小于69重量％关于嵌段共聚物的总重量，和（5）嵌段共聚物在苯乙烯中的5重量％溶液的粘度为至少5mPa.s但小于30mPa.s。该嵌段共聚物用作树脂的改性剂。

5. 发明申请

US20100154735A1 ENGINE BALANCER 有权
标题翻译：发动机平衡器
公开(公告)号：US20100154735A1
公开(公告)日：2010-06-24
申请号：US12637911
申请日：2009-12-15
申请人： Chiaki Kato , Kazuya Ito , Naohiro Koi , Sakumi Haseto , Eiji Wada , Masaaki Sato
发明人： Chiaki Kato , Kazuya Ito , Naohiro Koi , Sakumi Haseto , Eiji Wada , Masaaki Sato
IPC分类号： F02B75/06
CPC分类号： F16F15/267 , F16F2226/04 , F16F2230/06
摘要： An engine balancer includes a pair of balancer shafts and a balancer housing for housing the balancer shafts, and is placed in an oil pan at the bottom of an engine. The balancer housing includes a pair of front and rear bearing walls respectively supporting the balancer shafts with rolling bearings interposed therebetween. The bearing walls of the balancer housing are attached to bearing walls for a crankshaft. The housing body has an aperture at the top thereof. The aperture of the housing body is covered with a plate-shaped cover member thinner than a member forming the housing body.
摘要翻译：发动机平衡器包括一对平衡器轴和用于容纳平衡轴的平衡器壳体，并且放置在发动机底部的油底壳中。平衡器壳体包括一对前轴承壁和后轴承壁，分别支撑平衡轴，其间插入有滚动轴承。平衡器壳体的轴承壁连接到用于曲轴的轴承壁。壳体在其顶部具有孔。壳体的孔径被覆盖有比形成壳体主体的构件更薄的板状盖构件。

6. 发明授权

US06731057B2 Phosphors for fluorescent lamps 有权
标题翻译：荧光灯用荧光灯
公开(公告)号：US06731057B2
公开(公告)日：2004-05-04
申请号：US10105808
申请日：2002-03-21
申请人： Hisashi Yoshida , Maki Minamoto , Kazuya Ito , Yosuke Nishikage
发明人： Hisashi Yoshida , Maki Minamoto , Kazuya Ito , Yosuke Nishikage
IPC分类号： H01J1102
CPC分类号： C09K11/7734
摘要： A phosphor represented by the formula (1−x)CaO.EU(O).yMgO.nSiO2, wherein x, y and n represent number of moles, respectively, provides increased initial luminous intensity and exhibits superior sustainability of luminous intensity over long periods of use in a fluorescent lamp including the above phosphor.
摘要翻译：由式（1-x）CaO.EU（O）.MgO.nSiO 2表示的荧光体，其中x，y和n分别表示摩尔数，提供增加的初始发光强度，并且在长时间内表现出优异的发光强度的持续性在包括上述荧光体的荧光灯中使用。

7. 发明授权

US06654270B2 Directional coupling memory module 失效
公开(公告)号：US06654270B2
公开(公告)日：2003-11-25
申请号：US10191112
申请日：2002-07-10
申请人： Hideki Osaka , Toyohiko Komatsu , Takashi Tsunehiro , Koichi Kimura , Susumu Hatano , Kazuya Ito , Toshio Sugano
发明人： Hideki Osaka , Toyohiko Komatsu , Takashi Tsunehiro , Koichi Kimura , Susumu Hatano , Kazuya Ito , Toshio Sugano
IPC分类号： G11C502
CPC分类号： G11C5/063 , G11C5/04
摘要： Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.

8. 发明授权

US6122718A Column address counter with minus two subtractor for address compare 失效
标题翻译：列地址计数器，带负二位减法器，用于地址比较
公开(公告)号：US6122718A
公开(公告)日：2000-09-19
申请号：US988730
申请日：1997-12-11
申请人： Kazuya Ito
发明人： Kazuya Ito
IPC分类号： G11C7/10 , G06F12/02
CPC分类号： G11C7/1018
摘要： The present invention is a method and circuit for providing a burst address counter with a fast burst-done signal. In a preferred embodiment, a synchronous memory device includes a counter for producing a sequence of burst addresses, based on an external address. In addition, the counter drives the burst-done signal to indicate completion of the burst sequence. The counter includes a register for receiving the external address, an incrementor for advancing the external address to produce the next address of the sequence of burst addresses, a minus-two subtractor for determining a second-to-last burst address of the burst sequence, and a comparator. By utilizing the minus-two subtractor, the comparator can determine the end of the burst sequence earlier than conventional counters. This is because the minus-two subtractor determines the next-to-last address of the sequence, which allows the comparator to start asserting the burst-done signal at an earlier time.
摘要翻译：本发明是用于提供具有快速突发完成信号的突发地址计数器的方法和电路。在优选实施例中，同步存储器件包括用于基于外部地址产生脉冲串地址序列的计数器。此外，计数器驱动突发完成信号以指示突发序列的完成。计数器包括用于接收外部地址的寄存器，用于前进外部地址以产生突发地址序列的下一个地址的增量器，用于确定突发序列的第二至第突发地址的负二减法器，和比较器。通过利用负二减法器，比较器可以比常规计数器更早地确定突发序列的结束。这是因为负二减法器确定序列的下一个到最后的地址，这允许比较器在较早的时间开始断言突发完成信号。

9. 发明授权

US5441834A Process for fabricating phase shift mask and process of semiconductor integrated circuit device 失效
标题翻译：制造相移掩模和半导体集成电路器件的工艺
公开(公告)号：US5441834A
公开(公告)日：1995-08-15
申请号：US943002
申请日：1992-09-10
申请人： Toshitsugu Takekuma , Ii: Haruo , Kazuya Ito
发明人： Toshitsugu Takekuma , Ii: Haruo , Kazuya Ito
IPC分类号： G03F1/26 , G03F1/30 , G03F1/36 , G03F1/40 , G03F1/68 , G03F1/70 , G03F1/80 , G06F17/50 , H01L21/027 , G03F9/00
CPC分类号： G03F1/30 , G03F1/26 , Y10S430/143
摘要： When the data of a mask pattern of a phase shift mask is to be made, the pattern data is separated into a real pattern data layer having the data of real patterns and a phase shift pattern data layer having the data of phase shift patterns. After this, it is verified whether or not the mask pattern satisfies the regulation of the gap of in-phase patterns, in which lights having transmitted through patterns adjacent to each other are in phase. It is also verified whether or not the mask pattern satisfies the regulation of the gap of out-of-phase patterns, in which lights having transmitted through patterns adjacent to each other are out of phase.
摘要翻译：当要进行相移掩模的掩模图案的数据时，将图案数据分离成具有实数图案的实际图案数据层和具有相移图案的数据的相移图案数据层。此后，验证掩模图案是否满足彼此相邻的透过图案的光同相的同相图案的间隙的调节。还验证了掩模图案是否满足彼此相邻的具有透射图案的光异相的异相图案的间隙的调节。

10. 发明授权

US07257725B2 Memory system 失效
标题翻译：内存系统
公开(公告)号：US07257725B2
公开(公告)日：2007-08-14
申请号：US10294594
申请日：2002-11-15
申请人： Hideki Osaka , Toyohiko Komatsu , Masashi Horiguchi , Susumu Hatano , Kazuya Ito
发明人： Hideki Osaka , Toyohiko Komatsu , Masashi Horiguchi , Susumu Hatano , Kazuya Ito
IPC分类号： G06F1/00
CPC分类号： G06F13/4086
摘要： A clock is located at a position close to a plurality of memory modules connected to a memory controller and located away from the controller, and wiring is carried out so that read access is preferential for transmission of read data. With respect to write data, a delay amount corresponding to a round-trip propagation delay time to each of the modules is measured and writing of the write data is carried out while maintaining a known time relationship between the clock and data. To measure round-trip reflection, lines are wired between the modules and a location detection circuit in a 1:1 relationship, and the circuit measures a time taken from a signal output time of a driver having the same impedance as that of the wired lines to a reflected-wave reception time of a hysteresis receiver.
摘要翻译：时钟位于靠近与存储器控制器并且远离控制器的多个存储器模块的位置，并且执行布线，使得读取访问优先于读取数据的传输。对于写数据，测量对应于每个模块的往返传播延迟时间的延迟量，并且在保持时钟和数据之间的已知时间关系的同时执行写入数据的写入。为了测量往返反射，线路以1：1的关系连接到模块和位置检测电路之间，并且电路测量从具有与有线线路相同阻抗的驱动器的信号输出时间所花费的时间到滞后接收器的反射波接收时间。

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