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1. 发明授权

US5202969A Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively 失效
标题翻译：单片缓存缓冲器，用于基于位和位串的指示，有选择地写入回写和独占地将数据块部分写入主存储器
公开(公告)号：US5202969A
公开(公告)日：1993-04-13
申请号：US871906
申请日：1992-04-21
申请人： Katsuyuki Sato , Tadahiko Nishimukai , Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Hiroshi Fukuta , Takashi Kikuchi , Yasuhiko Saigou
发明人： Katsuyuki Sato , Tadahiko Nishimukai , Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Hiroshi Fukuta , Takashi Kikuchi , Yasuhiko Saigou
IPC分类号： G06F12/08 , G11C11/4096
CPC分类号： G06F12/0804 , G11C11/4096
摘要： In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.
摘要翻译：在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。在缓冲寄存器和数据存储器之间连接一个选择器。该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。这种布置为高速缓冲存储器提供部分写入功能。

2. 发明授权

US5146573A Single chip cache with partial-write circuit for transferring a preselected portion of data between memory and buffer register 失效
标题翻译：具有部分写入电路的单芯片缓存，用于在存储器和缓冲寄存器之间传输预选的数据部分
公开(公告)号：US5146573A
公开(公告)日：1992-09-08
申请号：US426781
申请日：1989-10-25
申请人： Katsuyuki Sato , Tadahiko Nishimukai , Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Hiroshi Fukuta , Takashi Kikuchi , Yasuhiko Saigou
发明人： Katsuyuki Sato , Tadahiko Nishimukai , Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Hiroshi Fukuta , Takashi Kikuchi , Yasuhiko Saigou
IPC分类号： G06F12/08 , G11C11/4096
CPC分类号： G11C11/4096 , G06F12/0804
摘要： In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.
摘要翻译：在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。在缓冲寄存器和数据存储器之间连接一个选择器。该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。这种布置为高速缓冲存储器提供部分写入功能。

3. 发明授权

US5193075A Static memory containing sense AMP and sense AMP switching circuit 失效
标题翻译：静态存储器包含检测AMP和感测AMP开关电路
公开(公告)号：US5193075A
公开(公告)日：1993-03-09
申请号：US490745
申请日：1990-03-08
申请人： Susumu Hatano , Kanji Oishi , Takashi Kikuchi , Yasuhiko Saigou , Hiroshi Fukuta , Kunio Uchiyama , Hirokazu Aoki , Osamu Nishii
发明人： Susumu Hatano , Kanji Oishi , Takashi Kikuchi , Yasuhiko Saigou , Hiroshi Fukuta , Kunio Uchiyama , Hirokazu Aoki , Osamu Nishii
IPC分类号： G11C11/419 , G06F12/08 , G11C7/06 , G11C11/40 , G11C11/41 , H01L27/10
CPC分类号： G11C7/065
摘要： A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and an output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.
摘要翻译：静态存储单元与字线和数据线连接。第一和第二开关串联连接在数据线和输出电路之间。读出放大器具有连接到所述第一和第二开关的公共连接点的输入/输出端子。第一开关与读出放大器的开始操作同步关闭，使得从读出放大器观察的数据线的寄生电容减小。为了将读出放大器的输出信号发送到输出电路，第二开关装置在预定的时间之后被接通。

4. 发明授权

US5267198A Static memory containing sense amp and sense amp switching circuit 失效
标题翻译：包含读出放大器和感测放大器开关电路的静态存储器
公开(公告)号：US5267198A
公开(公告)日：1993-11-30
申请号：US953747
申请日：1992-09-29
申请人： Susumu Hatano , Kanji Oishi , Takashi Kikuchi , Yasuhiko Saigou , Hiroshi Fukuta , Kunio Uchiyama , Hirokazu Aoki , Osamu Nishii
发明人： Susumu Hatano , Kanji Oishi , Takashi Kikuchi , Yasuhiko Saigou , Hiroshi Fukuta , Kunio Uchiyama , Hirokazu Aoki , Osamu Nishii
IPC分类号： G11C11/419 , G06F12/08 , G11C7/06 , G11C11/40 , G11C11/41 , H01L27/10
CPC分类号： G11C7/065
摘要： A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and on output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.
摘要翻译：静态存储单元与字线和数据线连接。第一和第二开关串联连接在数据线和输出电路之间。读出放大器具有连接到所述第一和第二开关的公共连接点的输入/输出端子。第一开关与读出放大器的开始操作同步关闭，使得从读出放大器观察的数据线的寄生电容减小。为了将读出放大器的输出信号发送到输出电路，第二开关装置在预定的时间之后被接通。

5. 发明授权

US5140681A Multi-processing system and cache apparatus for use in the same 失效
标题翻译：多处理系统及其使用的缓存设备
公开(公告)号：US5140681A
公开(公告)日：1992-08-18
申请号：US355680
申请日：1989-05-23
申请人： Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Takashi Kikuchi , Hiroshi Fukuta , Yasuhiko Saigou
发明人： Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Takashi Kikuchi , Hiroshi Fukuta , Yasuhiko Saigou
IPC分类号： G06F12/08 , G06F15/16
CPC分类号： G06F12/0815 , G06F2212/621
摘要： A main memory is subdivided into a shared region to undergo a write access from a plurality of processors and an input/output device and a plurality of private regions to undergo a write access only from the associated processor. Each of the cache devices includes a region discriminating circuit for determining whether an address generated from the processor is to be employed for an access to the shared region or to the private regions. If the access is to be conducted to the shared region, the cache devices operate according to the write-through method. On the other hand, if the access is to be conducted to the private region, the cache devices operate according to the copy-back method. When the processor or the input/output device rewrites data in the shared region of the main memory, the stored data of the shared region in the cache device of the processor is invalidated.

6. 发明授权

US5283886A Multiprocessor cache system having three states for generating invalidating signals upon write accesses 失效
标题翻译：具有三种状态的多处理器缓存系统，用于在写访问时产生无效信号
公开(公告)号：US5283886A
公开(公告)日：1994-02-01
申请号：US950746
申请日：1992-09-24
申请人： Osamu Nishii , Kunio Uchiyama , Hirokazu Aoki , Kanji Oishi , Jun Kitano , Susumu Hatano
发明人： Osamu Nishii , Kunio Uchiyama , Hirokazu Aoki , Kanji Oishi , Jun Kitano , Susumu Hatano
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0833
摘要： Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating signal to the address bus and the invalidating signal line, respectively. When the write access from the first processor misses the first cache, a data of one block is block-transferred from the main memory to the first cache, and the invalidating signal is outputted. After this, the first cache executes the write of the data in the transfer block. In case the first and second caches hold the data in the third state relating to the pertinent address when an address of an access request is fed to the address bus (123), the pertinent cache writes back the pertinent data in the main memory.
摘要翻译：这里公开了一种多处理器系统，其包括第一和第二处理器（1001和1002），第一和第二高速缓冲存储器（100：＃1和＃2），地址总线（123），数据总线（126），无效信号线（PURGE：131）和主存储器（1004）。第一和第二高速缓存存储器通过复制方法操作。第一高速缓存（100：＃1）的数据的状态存在于从由无效的第一状态，有效和未更新的第二状态以及有效和更新的第三状态组成的组中选择的一个状态中。第二个缓存（100：＃2）被构造成像第一个缓存。当第一处理器的写入访问第一高速缓存时，第一高速缓存的数据的状态从第二状态转移到第三状态，并且第一高速缓存将写入命中的地址和无效信号输出到地址总线和无效信号线。当来自第一处理器的写访问错过第一高速缓存时，一个块的数据被从主存储器块传输到第一高速缓存，并且输出无效信号。之后，第一个缓存执行传输块中数据的写入。在第一和第二高速缓冲存储器将存取请求地址与相关地址相关的第三状态的数据保存到地址总线（123）的情况下，相关高速缓冲存储器将相关数据写回到主存储器中。

7. 发明申请

US20090325034A1 SEPARATOR FOR HUMIDIFIER, HUMIDIFIER, AND FUEL CELL SYSTEM COMPRISING THE HUMIDIFIER 失效
标题翻译：用于除湿器，除湿器和包含增湿器的燃料电池系统的分离器
公开(公告)号：US20090325034A1
公开(公告)日：2009-12-31
申请号：US12375661
申请日：2007-12-12
申请人： Susumu Kobayashi , Susumu Hatano
发明人： Susumu Kobayashi , Susumu Hatano
IPC分类号： H01M8/04 , F22D1/30
CPC分类号： H01M8/04149 , F24F2003/1435
摘要： A separator for use in a humidifying device includes: main surfaces contacting steam permeable membranes (2), respectively; a fluid channel (3, 4) formed by concave portions (66, 81) of a convex-concave portion formed on each of the main surfaces; and an elastic layer (1a, 1c) formed up to at least a certain depth from tip ends of convex portions (67, 82) of the convex-concave portion.
摘要翻译：用于加湿装置的分离器包括：主表面分别接触透湿膜（2）; 由形成在每个主表面上的凸凹部分的凹部（66,81）形成的流体通道（3,4）以及从凸凹部的凸部（67,82）的前端形成至少一定深度的弹性层（1a，1c）。

8. 发明授权

US07515157B2 Data transmission device, data transfer system and method 失效
标题翻译：数据传输装置，数据传输系统及方法
公开(公告)号：US07515157B2
公开(公告)日：2009-04-07
申请号：US10333132
申请日：2000-12-14
申请人： Toyohiko Komatsu , Hideki Osaka , Masashi Horiguchi , Susumu Hatano , Kazuya Ito
发明人： Toyohiko Komatsu , Hideki Osaka , Masashi Horiguchi , Susumu Hatano , Kazuya Ito
IPC分类号： G06F13/14
CPC分类号： H04L12/40
摘要： A data transfer method is executed to transit a three-state transmitting circuit from a high-impedance state into a data output state, transmit a preamble (dummy data) onto a bus, and sequentially transmit the essential data. The shortening of a waveform caused in the first data piece after the transition from the high-impedance state into the data output state is executed against the preamble and no shortening of a waveform is not brought about in the essential data subsequent to the preamble. This makes it possible to exclude the limitation on speeding up the data transfer imposed by the shortening of the waveform.
摘要翻译：执行数据传送方法以将三状态发送电路从高阻抗状态转移到数据输出状态，将前导码（虚拟数据）发送到总线上，并且顺序发送基本数据。在从高阻抗状态转换到数据输出状态之后，在第一数据段中引起的波形的缩短针对前同步码执行，并且在前导码之后的基本数据中不会引起波形的缩短。这使得可以排除由于缩短波形而加速数据传输的限制。

9. 发明申请

US20060130314A1 Method for manufacturing a stator core for a dynamoelectric machine 有权
公开(公告)号：US20060130314A1
公开(公告)日：2006-06-22
申请号：US11354943
申请日：2006-02-16
申请人： Yoshihiro Harada , Susumu Hatano , Kensaku Kuroki , Atsushi Oohashi
发明人： Yoshihiro Harada , Susumu Hatano , Kensaku Kuroki , Atsushi Oohashi
IPC分类号： H02K15/14 , H01F7/06
CPC分类号： H02K15/024 , H02K1/16 , H02K15/026 , Y10T29/49009 , Y10T29/49012 , Y10T29/49073 , Y10T29/49075 , Y10T29/49078 , Y10T29/53143
摘要： A cylindrical laminated body is prepared by winding into a helical shape a continuous first sheet formed by press-punching from a thin first magnetic steel sheet material. A second sheet having a predetermined length is prepared by press-punching from a thicker second magnetic steel sheet material. Next, chamfered portions are formed on edge portions of second recess portions by chamfering the second sheet. Then, the second sheet is bent into an annular shape and the second sheets bent into the annular shape are stacked on both axial ends of the laminated body and integrated by laser welding.

10. 发明授权

US06983023B2 Data transmission system of directional coupling type using forward wave and reflection wave 失效
公开(公告)号：US06983023B2
公开(公告)日：2006-01-03
申请号：US09908710
申请日：2001-07-20
申请人： Hideki Osaka , Susumu Hatano , Toyohiko Komatsu , Tsutomu Hara
发明人： Hideki Osaka , Susumu Hatano , Toyohiko Komatsu , Tsutomu Hara
IPC分类号： H04B3/00
CPC分类号： H04L25/028 , G11C7/1051 , G11C7/1078 , G11C7/1084 , H01L2224/16225 , H01L2924/00014 , H01L2924/13091 , H01L2924/15192 , H01L2924/15311 , H04B3/00 , H04L25/0266 , H04L25/0292 , H01L2924/00 , H01L2224/0401
摘要： A memory module bus system using a plurality of directional couplers to permit high-density packaging. A wiring line (main line) extending from a main controller and cooperating with a sub coupling line to form a directional coupler is open-ended or short-circuited to ensure that a forward wave and a reflection wave can be used to generate signals in opposite directions of the directional coupler. Memory modules are connected to opposite ends of the sub coupling line. The line length of the coupler can be half the pitch between the memory modules.

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