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1. 发明授权

US07262997B2 Process for operating an electronic device including a memory array and conductive lines 有权
标题翻译：用于操作包括存储器阵列和导线的电子设备的工艺
公开(公告)号：US07262997B2
公开(公告)日：2007-08-28
申请号：US11188898
申请日：2005-07-25
申请人： Jane A. Yater , Gowrishankar L. Chindalore , Cheong M. Hong
发明人： Jane A. Yater , Gowrishankar L. Chindalore , Cheong M. Hong
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/10
摘要： An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.
摘要翻译：电子电路可以包括第一存储单元和第二存储单元。在一个实施例中，第一和第二存储器单元的源极/漏极区域可彼此电连接。源极/漏极区域可以电浮动，而不管载流子流过存储器单元的沟道区域的方向如何。在另一个实施例中，与第一存储器单元相比，第一存储单元可以电连接到第一栅极线，并且第二存储单元可以电连接到更多数量的栅极线。在另一方面，第一和第二存储器单元连接到相同的位线。当编程或读取第一存储器单元或第二存储单元或其任何组合时，这种位线可以电浮动。

2. 发明授权

US07471560B2 Electronic device including a memory array and conductive lines 有权
标题翻译：电子设备包括存储器阵列和导线
公开(公告)号：US07471560B2
公开(公告)日：2008-12-30
申请号：US11834391
申请日：2007-08-06
申请人： Jane A. Yater , Gowrishankar L. Chindalore , Cheong M. Hong
发明人： Jane A. Yater , Gowrishankar L. Chindalore , Cheong M. Hong
IPC分类号： G11C11/34
CPC分类号： G11C16/10
摘要： An electronic circuit can include a first memory cell and a second memory cell. In one embodiment, source/drain regions of the first and second memory cells can be electrically connected to each other. The source/drain regions may electrically float regardless of direction in which carriers flow through channel regions of the memory cells. In another embodiment, the first memory cell can be electrically connected to a first gate line, and the second memory cell can be electrically connected to a greater number of gate lines as compared to the first memory cell. In another aspect, the first and second memory cells are connected to the same bit line. Such bit line can electrically float when programming or reading the first memory cell or the second memory cell or any combination thereof.
摘要翻译：电子电路可以包括第一存储单元和第二存储单元。在一个实施例中，第一和第二存储器单元的源极/漏极区域可彼此电连接。源极/漏极区域可以电浮动，而不管载流子流过存储器单元的沟道区域的方向如何。在另一个实施例中，与第一存储器单元相比，第一存储单元可以电连接到第一栅极线，并且第二存储单元可以电连接到更多数量的栅极线。在另一方面，第一和第二存储器单元连接到相同的位线。当编程或读取第一存储器单元或第二存储单元或其任何组合时，这种位线可以电浮动。

3. 发明授权

US07256454B2 Electronic device including discontinuous storage elements and a process for forming the same 有权
标题翻译：包括不连续存储元件的电子设备及其形成方法
公开(公告)号：US07256454B2
公开(公告)日：2007-08-14
申请号：US11188953
申请日：2005-07-25
申请人： Jane A. Yater , Gowrishankar L. Chindalore , Cheong M. Hong
发明人： Jane A. Yater , Gowrishankar L. Chindalore , Cheong M. Hong
IPC分类号： H01L29/423
CPC分类号： H01L29/7887 , B82Y10/00 , G11C16/0458 , G11C16/0475 , G11C16/0491 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11556 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/42348 , H01L29/42352 , H01L29/7923 , H01L29/7926
摘要： An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate that includes a trench extending into a semiconductor material. The trench can include a ledge and a bottom, wherein the bottom lies at a depth deeper than the ledge. The electronic device can include discontinuous storage elements, wherein a trench portion of the discontinuous storage elements lies within the trench. Gate electrodes may lie adjacent to walls of the trench. In a particular embodiment, a portion of a channel region within a memory cell may not be covered by a gate electrode. In another embodiment, a doped region may underlie the ledge and allow for memory cells to be formed at different elevations within the trench. In other embodiment, a process can be used to form the electronic device.
摘要翻译：电子设备可以包括位于沟槽内的不连续存储元件。在一个实施例中，电子设备可以包括包括延伸到半导体材料中的沟槽的衬底。沟槽可以包括凸缘和底部，其中底部位于比凸缘更深的深度。电子设备可以包括不连续的存储元件，其中不连续存储元件的沟槽部分位于沟槽内。栅电极可以邻近沟槽的壁。在特定实施例中，存储器单元内的通道区域的一部分可能不被栅电极覆盖。在另一个实施例中，掺杂区域可以在凸缘的下面，并允许在沟槽内的不同高度处形成存储单元。在其他实施例中，可以使用一种工艺来形成电子设备。

4. 发明授权

US08679912B2 Semiconductor device having different non-volatile memories having nanocrystals of differing densities and method therefor 有权
标题翻译：具有具有不同密度的纳米晶体的不同非易失性存储器的半导体器件及其方法
公开(公告)号：US08679912B2
公开(公告)日：2014-03-25
申请号：US13362697
申请日：2012-01-31
申请人： Sung-Taeg Kang , Gowrishankar L. Chindalore , Brian A. Winstead , Jane A. Yater
发明人： Sung-Taeg Kang , Gowrishankar L. Chindalore , Brian A. Winstead , Jane A. Yater
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42332
摘要： A method for forming a semiconductor device includes forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region and has a first density; and, after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region, wherein the first plurality of nanocrystals together with the second plurality of nanocrystals in the second region result in a second density, wherein the second density is greater than the first density.
摘要翻译：一种形成半导体器件的方法包括在具有第一区域和第二区域的衬底的表面上形成第一多个纳米晶体，其中所述第一多个纳米晶体形成在所述第一区域和所述第二区域中，并具有第一密度 ; 并且在形成所述第一多个纳米晶体之后，在所述第二区域而不是所述第一区域的所述衬底的表面上形成第二多个纳米晶体，其中所述第一多个纳米晶体与所述第二区域中的所述第二多个纳米晶体结果在第二密度中，其中第二密度大于第一密度。

5. 发明授权

US06969883B2 Non-volatile memory having a reference transistor 有权
标题翻译：具有参考晶体管的非易失性存储器
公开(公告)号：US06969883B2
公开(公告)日：2005-11-29
申请号：US10950855
申请日：2004-09-27
申请人： Gowrishankar L. Chindalore , Rajesh A. Rao , Jane A. Yater
发明人： Gowrishankar L. Chindalore , Rajesh A. Rao , Jane A. Yater
IPC分类号： G11C5/00 , G11C16/28 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L29/76
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/28 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/11573
摘要： A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46). The read control circuit (42) senses a drain current of the reference transistor (46) and adjusts the gate bias voltage to maintain the reference current at a substantially constant value relative to the cell current.
摘要翻译：非易失性存储器（30）包括纳米晶体存储单元（50,51,53）。存储单元晶体管（50,51,53）的编程和擦除阈值电压作为编程/擦除操作的次数增加。在读取操作期间，参考晶体管（46）提供用于与单元电流进行比较的参考电流。除了参考晶体管（46）不包括纳米晶体之外，参考晶体管（46）由与制造存储单元晶体管（50,51,53）类似的工艺制成。通过使用类似的工艺来使参考晶体管（46）和存储单元晶体管（50,51,53）同时工作，参考晶体管（46）的阈值电压将跟踪存储单元晶体管（50）的阈值电压偏移，51,53）。提供读控制电路（42）以偏置参考晶体管（46）的栅极。读取控制电路（42）感测参考晶体管（46）的漏极电流并调整栅极偏置电压，以使参考电流相对于单元电流保持在基本恒定的值。

6. 发明授权

US07064030B2 Method for forming a multi-bit non-volatile memory device 有权
标题翻译：用于形成多位非易失性存储器件的方法
公开(公告)号：US07064030B2
公开(公告)日：2006-06-20
申请号：US10961014
申请日：2004-10-08
申请人： Gowrishankar L. Chindalore , Jane A. Yater
发明人： Gowrishankar L. Chindalore , Jane A. Yater
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： Forming a non-volatile memory device includes providing a semiconductor substrate, forming a masking layer having a first plurality of openings overlying the semiconductor substrate, forming diffusion regions in the semiconductor substrate at locations determined by the masking layer, forming a dielectric within the first plurality of openings, removing the masking layer to form a second plurality of openings, forming sacrificial spacers along edges of the second plurality of openings and adjacent to the dielectric, forming a separating dielectric to separate the sacrificial spacers within each of the second plurality of openings, forming a sacrificial protection layer overlying the separating dielectric, removing the sacrificial spacers, removing the sacrificial protection layer, forming at least two memory storage regions within each of the second plurality of openings, and forming a common control electrode overlying the at least two memory storage regions. This device may be used, for example, in a VGA memory array.
摘要翻译：形成非易失性存储器件包括提供半导体衬底，形成具有覆盖半导体衬底的第一多个开口的掩模层，在由掩模层确定的位置处在半导体衬底中形成扩散区，在第一多个的开口，去除所述掩模层以形成第二多个开口，沿着所述第二多个开口的边缘并且邻近所述电介质形成牺牲隔离物，形成分离电介质以在所述第二多个开口的每一个内分离所述牺牲隔离物，形成覆盖所述分离电介质的牺牲保护层，去除所述牺牲隔离物，去除所述牺牲保护层，在所述第二多个开口的每一个内形成至少两个存储器存储区域，以及形成覆盖所述至少两个存储器存储器地区。该装置可以用于例如VGA存储器阵列中。

7. 发明授权

US06964902B2 Method for removing nanoclusters from selected regions 失效
公开(公告)号：US06964902B2
公开(公告)日：2005-11-15
申请号：US10787510
申请日：2004-02-26
申请人： Robert F. Steimle , Jane A. Yater , Gowrishankar L. Chindalore , Craig T. Swift , Steven G. H. Anderson , Ramachandran Muralidhar
发明人： Robert F. Steimle , Jane A. Yater , Gowrishankar L. Chindalore , Craig T. Swift , Steven G. H. Anderson , Ramachandran Muralidhar
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/336 , H01L21/44 , H01L21/8247 , H01L27/105 , H01L29/792
CPC分类号： H01L21/32135 , B82Y10/00 , H01L21/28273 , H01L21/32134 , H01L27/105 , H01L27/11521 , H01L27/11526
摘要： Nanoclusters are blanket deposited on an integrated circuit and then removed from regions where the nanoclusters are not desired. A sacrificial layer is formed in those regions where the nanoclusters are not desired prior to the blanket deposition. The nanoclusters and the sacrificial layer are then removed. In one form, the sacrificial layer includes a deposited nitride containing or oxide containing layer. Alternatively, the sacrificial layer includes at least one of a pad oxide or a pad nitride layer previously used to form isolation regions in the substrate. Nanocluster devices and non-nanocluster devices may then be integrated onto the same integrated circuit. The use of a sacrificial layer protects underlying layers thereby preventing the degradation of performance of the subsequently formed non-nanocluster devices.

8. 发明授权

US06955967B2 Non-volatile memory having a reference transistor and method for forming 有权
标题翻译：具有参考晶体管的非易失性存储器及其形成方法
公开(公告)号：US06955967B2
公开(公告)日：2005-10-18
申请号：US10609361
申请日：2003-06-27
申请人： Gowrishankar L. Chindalore , Rajesh A. Rao , Jane A. Yater
发明人： Gowrishankar L. Chindalore , Rajesh A. Rao , Jane A. Yater
IPC分类号： G11C5/00 , G11C16/28 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L29/76
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/28 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/11573
摘要： A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46). The read control circuit (42) senses a drain current of the reference transistor (46) and adjusts the gate bias voltage to maintain the reference current at a substantially constant value relative to the cell current.
摘要翻译：非易失性存储器（30）包括纳米晶体存储单元（50,51,53）。存储单元晶体管（50,51,53）的编程和擦除阈值电压作为编程/擦除操作的次数增加。在读取操作期间，参考晶体管（46）提供用于与单元电流进行比较的参考电流。除了参考晶体管（46）不包括纳米晶体之外，参考晶体管（46）由与制造存储单元晶体管（50,51,53）类似的工艺制成。通过使用类似的工艺来使参考晶体管（46）和存储单元晶体管（50,51,53）同时工作，参考晶体管（46）的阈值电压将跟踪存储单元晶体管（50）的阈值电压偏移，51,53）。提供读控制电路（42）以偏置参考晶体管（46）的栅极。读取控制电路（42）感测参考晶体管（46）的漏极电流并调整栅极偏置电压，以使参考电流相对于单元电流保持在基本恒定的值。

9. 发明授权

US06839280B1 Variable gate bias for a reference transistor in a non-volatile memory 有权
标题翻译：非易失性存储器中的参考晶体管的可变栅极偏置
公开(公告)号：US06839280B1
公开(公告)日：2005-01-04
申请号：US10609359
申请日：2003-06-27
申请人： Gowrishankar L. Chindalore , Rajesh A. Rao , Jane A. Yater
发明人： Gowrishankar L. Chindalore , Rajesh A. Rao , Jane A. Yater
IPC分类号： G11C20060101 , G11C11/34 , G11C16/00 , G11C16/06 , G11C16/28 , H01L21/28 , H01L21/8247
CPC分类号： B82Y10/00 , G11C16/28 , G11C2216/06 , H01L21/28273 , H01L27/11531
摘要： A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46). The read control circuit (42) senses a drain current of the reference transistor (46) and adjusts the gate bias voltage to maintain the reference current at a substantially constant value relative to the cell current.
摘要翻译：非易失性存储器（30）包括纳米晶体存储单元（50,51,53）。存储单元晶体管（50,51,53）的编程和擦除阈值电压作为编程/擦除操作的次数增加。在读取操作期间，参考晶体管（46）提供用于与单元电流进行比较的参考电流。除了参考晶体管（46）不包括纳米晶体之外，参考晶体管（46）由与制造存储单元晶体管（50,51,53）类似的工艺制成。通过使用类似的工艺来使参考晶体管（46）和存储单元晶体管（50,51,53）同时工作，参考晶体管（46）的阈值电压将跟踪存储单元晶体管（50）的阈值电压偏移，51,53）。提供读控制电路（42）以偏置参考晶体管（46）的栅极。读取控制电路（42）感测参考晶体管（46）的漏极电流并调整栅极偏置电压，以使参考电流相对于单元电流保持在基本恒定的值。

10. 发明授权

US07285819B2 Nonvolatile storage array with continuous control gate employing hot carrier injection programming 有权
公开(公告)号：US07285819B2
公开(公告)日：2007-10-23
申请号：US11188582
申请日：2005-07-25
申请人： Gowrishankar L. Chindalore , Cheong M. Hong , Craig T. Swift
发明人： Gowrishankar L. Chindalore , Cheong M. Hong , Craig T. Swift
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L29/4232 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7923
摘要： An array of storage cells include a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.

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