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1. 发明授权

US6061268A 0.7V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique 有权
标题翻译：具有采用部分耗尽的SOI CMOS动态阈值技术的单位同步读写访问（SBLSRWA）功能的0.7V双端口6T SRAM存储单元结构
公开(公告)号：US6061268A
公开(公告)日：2000-05-09
申请号：US427727
申请日：1999-10-27
申请人： James B. Kuo , Sheng-Che Liu
发明人： James B. Kuo , Sheng-Che Liu
IPC分类号： G11C8/16 , G11C11/412 , G11C11/00
CPC分类号： G11C8/16 , G11C11/412
摘要： This invention discloses a novel low-voltage two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access capability using partially-depleted SOI CMOS dynamic-threshold technique. With an innovative approach by connecting the body terminal of an NMOS device in the latch and the write access pass transistor to the write word line, this 6T memory cell can be used to provide SBLSRWA capability for 0.7 V two-port SOI CMOS VLSI SRAM as verified by MEDICI results.
摘要翻译：本发明公开了一种采用部分耗尽的SOI CMOS动态阈值技术的新型低电压双端口6T SRAM存储单元结构，具有单位线同时读 - 写访问能力。通过将锁存器中的NMOS器件的主体端子和写入通道晶体管连接到写入字线的创新方法，该6T存储器单元可用于为0.7V双端口SOI CMOS VLSI SRAM提供SBLSRWA能力，作为通过MEDICI结果验证。

2. 发明授权

US06240004B1 Low-voltage content addressable memory cell with a fast tag-compare capability using partially-depleted SOI CMOS dynamic-threshold techniques 有权
标题翻译：低电压内容可寻址存储单元，具有使用部分耗尽的SOI CMOS动态阈值技术的快速标签比较能力
公开(公告)号：US06240004B1
公开(公告)日：2001-05-29
申请号：US09597275
申请日：2000-06-19
申请人： James B. Kuo , Sheng-Che Liu
发明人： James B. Kuo , Sheng-Che Liu
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： This invention discloses a content addressable memory (CAM) cell having a SRAM portion and a tag-compare portion. The tag-compare portion includes six NMOS transistors, designated as M7 to M12, wherein a source of M7 is connected to a drain of M8, a drain of M7 is connected to a match line ML, a source of M8 is grounded; a body of M7 and a body of M8 are tied together at a source of M11, a gate of M7 and a gate of M11 are tied together to a first node n1, a gate of M8 and a drain of M11 are connected to a first digit line DLB; and a source of M9 is connected to a drain of M10, a drain of M9 is connected to said match line ML, a source of M10 is grounded; a body of M9 and a body of M10 are tied together at a source of M12, a gate of M9 and a gate of M12 are tied together to a second node n2, a gate of M10 and a drain of M12 are connected to a second digit line DL. The first and second nodes n1 and n2 are internal storage nodes of the SRAM portion.
摘要翻译：本发明公开了一种具有SRAM部分和标签比较部分的内容寻址存储器（CAM）单元。标签比较部分包括六个称为M7至M12的NMOS晶体管，其中M7的源极连接到M8的漏极，M7的漏极连接到匹配线ML，M8的源极接地; M7的主体和M8的主体在M11的源处连接在一起，M7的门和M11的门被连接到第一节点n1，M8的门和M11的漏极连接到第一节点数字线DLB; 并且M9的源极连接到M10的漏极，M9的漏极连接到所述匹配线ML，M10的源极接地; M9的主体和M10的主体在M12的源极处连接在一起，M9的门和M12的门被连接在一起到第二节点n2，M10的门和M12的漏极连接到第二个数字线DL。第一和第二节点n1和n2是SRAM部分的内部存储节点。

3. 发明授权

US6118689A Two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability 失效
标题翻译：双端口6T CMOS SRAM单元结构，用于具有单位线同时读写访问（SBLSRWA）能力的低压VLSI SRAM
公开(公告)号：US6118689A
公开(公告)日：2000-09-12
申请号：US427728
申请日：1999-10-27
申请人： James B. Kuo , Bo-Ting Wang
发明人： James B. Kuo , Bo-Ting Wang
IPC分类号： G11C8/16 , G11C11/412 , G11C11/00
CPC分类号： G11C11/412 , G11C8/16
摘要： This invention reports a two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability. With an unique structure by connecting the source terminal of an NMOS device in the SRAM cell to the write word line, this SRAM cell can be used to provide SBLSRWA capability for 1V two-port VLSI SRAM as verified by SPICE results.
摘要翻译：本发明报告了具有单位线同时读写访问（SBLSRWA）功能的低压VLSI SRAM的双端口6T CMOS SRAM单元结构。通过将SRAM单元中的NMOS器件的源极端子连接到写入字线，具有独特的结构，该SRAM单元可用于为SPICE结果验证的1V双端口VLSI SRAM提供SBLSRWA功能。

4. 发明授权

US5973514A 1.5V bootstrapped all-N-logic true-single-phase CMOS dynamic logic circuit suitable for low supply voltage and high speed pipelined system operation 失效
标题翻译： 1.5V自举全N逻辑真相单相CMOS动态逻辑电路适用于低电源电压和高速流水线系统运行
公开(公告)号：US5973514A
公开(公告)日：1999-10-26
申请号：US977076
申请日：1997-11-24
申请人： James B. Kuo , Jea-Hong Lou
发明人： James B. Kuo , Jea-Hong Lou
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： This invention presents an all-N-logic true-single-phase CMOS dynamic logic circuit for high speed operation with a low supply voltage, in which a bootstrapped circuit containing a bootstrap capacitor, an inverter and a PMOS transistor is incorporated to a conventional non-inverting N1-block.
摘要翻译：本发明提供了一种全N逻辑的真正单相CMOS动态逻辑电路，用于具有低电源电压的高速操作，其中包含自举电容器，反相器和PMOS晶体管的自举电路并入到常规非 - 反转N1块。

5. 发明授权

US5729165A 1.5v full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage deep-submicron CMOS VLSI 失效
标题翻译： 1.5V全摆幅自举CMOS大电容负载驱动电路适用于低电压深亚微米CMOS VLSI
公开(公告)号：US5729165A
公开(公告)日：1998-03-17
申请号：US627482
申请日：1996-04-04
申请人： Jea Hong Lou , James B. Kuo
发明人： Jea Hong Lou , James B. Kuo
IPC分类号： H03K19/017 , H03B1/00
CPC分类号： H03K19/01714
摘要： A 1.5V full-swing bootstrapped CMOS large capacitive-load driver circuit using two bootstrap capacitors to enhance the switching speed for low-voltage deep-submicron CMOS VLSI. For a supply voltage of 1.5V, the full-swing bootstrapped CMOS driver circuit shows a 2.2 times improvement in switching speed in driving a capacitive load of 10 pF as compared to the conventional CMOS driver circuit. Even for a supply voltage of 1V, this full-swing bootstrapped CMOS large capacitive-load driver circuit is still advantageous.
摘要翻译：一个采用两个自举电容的1.5V全摆幅自举CMOS大容性负载驱动电路，以提高低电压深亚微米CMOS VLSI的开关速度。对于1.5V的电源电压，与常规CMOS驱动器电路相比，全摆幅自举CMOS驱动器电路在驱动10 pF的电容性负载时的开关速度提高了2.2倍。即使是1V的电源电压，这种全摆幅自举CMOS大电容负载驱动电路仍然是有利的。

6. 发明授权

US5898333A 1.5 bootstrapped pass-transistor-based Manchester-carry-chain circuit suitable for low-voltage CMOS VLSI 失效
标题翻译： 1.5自适应基于传输晶体管的曼彻斯特携带链电路适用于低压CMOS VLSI
公开(公告)号：US5898333A
公开(公告)日：1999-04-27
申请号：US953542
申请日：1997-10-20
申请人： James B. Kuo , Jea-Hong Lou
发明人： James B. Kuo , Jea-Hong Lou
IPC分类号： G06F7/50 , G06F7/503 , H03K17/16
CPC分类号： G06F7/503 , G06F2207/3872
摘要： This invention discloses a 1.5 V bootstrapped pass-transistor-based Manchester-carry-chain circuit suitable for CMOS VLSI using a low supply voltage, in which a bootstrapper circuit is incorporated to enhance the speed performance of the conventional Manchester-carry-chain circuit, which is composed. The bootstrapper circuit contains two P-type metal-oxide-semiconductor (PMOS) transistors, one N-type metal-oxide-semiconductor (NMOS) transistor; a capacitor device, and an inverter. The bootstrapper circuit provides an output having a voltage overshoot, as a carry propagation signal, to the gate of a pass transistor of the Manchester-carry-chain circuit.
摘要翻译：本发明公开了一种适用于使用低电源电压的CMOS VLSI的1.5V自举基于传输晶体管的曼彻斯特携带链电路，其中引入自举电路以增强传统的曼彻斯特携带链电路的速度性能，这是组成的。自举电路包含两个P型金属氧化物半导体（PMOS）晶体管，一个N型金属氧化物半导体（NMOS）晶体管; 电容器装置和逆变器。自举电路提供具有电压过冲作为进位传播信号的输出到曼彻斯特携带链电路的传输晶体管的栅极。

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