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1. 发明授权

US5166547A Programmable DCVS logic circuits 失效
标题翻译：可编程DCVS逻辑电路
公开(公告)号：US5166547A
公开(公告)日：1992-11-24
申请号：US711487
申请日：1991-06-05
申请人： Jacquelin Babakanian , James W. Davis , Mark S. Garvin , Kim P. Liew , Yoav Medan , Nandor G. Thoma
发明人： Jacquelin Babakanian , James W. Davis , Mark S. Garvin , Kim P. Liew , Yoav Medan , Nandor G. Thoma
IPC分类号： H01L21/82 , H01L23/525 , H01L27/118 , H03K19/0952 , H03K19/173
CPC分类号： H01L23/5258 , H03K19/1735 , H03K19/1738 , H01L2924/0002 , H01L2924/3011
摘要： A basic tree construction, from which differential cascode voltage switch (DCVS) circuits having variable logic personality can be formed, contains n (>2) rows of differentially associated semiconductor device pairs spanned by n pairs of complementary input conductor leads, and a load circuit coupled to drain terminals of devices in the nth row. The nth row contains 2 device pairs and each other row contains 2.sup.i-1 device pairs (i=1, 2, . . . , n-1). Connections between source and drain terminals of devices in successive rows are predefined from the 1st to the n-1st row and variably definable between the n-1st and nth rows. Connections between input conductors and device gate terminals are predefined in each row other than the nth row, and variably definable in the nth row. Upon selectively defining a set of variable connections relative to the n-1st and nth rows the logic personality of the tree is selected to conform to any one of all possible functions of n variables. Logic function personalization is established in one embodiment by altering materials at discrete points in a space between n-1st and nth rows. In another embodiment, personalization is established by altering signals stored by latch devices in the space between the n-1st and nth rows which control gating device adjacently positioned to form conductive connections corresponding to those formed by altering materials in the first embodiment.
摘要翻译：可以形成具有可变逻辑特性的差分共源共栅电压开关（DCVS）电路的基本树结构包含由n对互补输入导体引线跨越的n（> 2）个由差分相关的半导体器件对构成的行，负载电路耦合到第n行的器件的漏极端子。第n行包含2个设备对，每行包含2i-1个设备对（i = 1,2，...，n-1）。在连续行中的设备的源极和漏极端子之间的连接从第一行到第n行预定义，并且可以在第n-1行和第n行之间可变地定义。输入导体和器件栅极端子之间的连接在除第n行以外的每行中预定义，并且在第n行中可变地定义。在选择性地定义相对于第n-1和n行的一组可变连接时，选择树的逻辑个性以符合n个变量的所有可能函数中的任何一个。在一个实施例中通过在第n-1和第n行之间的空间中的离散点处改变材料来建立逻辑功能个性化。在另一个实施例中，通过在第n-1行和第n行之间的空间中改变由锁存装置存储的信号来建立个性化，所述信号控制门控装置相邻定位以形成对应于在第一实施例中通过改变材料形成的导电连接的导电连接。

2. 发明授权

US5299136A Fully testable DCVS circuits with single-track global wiring 失效
标题翻译：具有单轨全球接线的完全可测试的DCVS电路
公开(公告)号：US5299136A
公开(公告)日：1994-03-29
申请号：US711466
申请日：1991-06-05
申请人： Jacquelin Babakanian , James W. Davis , Mark S. Garvin , Robert M. Swanson , Nandor G. Thoma , David M. Wu
发明人： Jacquelin Babakanian , James W. Davis , Mark S. Garvin , Robert M. Swanson , Nandor G. Thoma , David M. Wu
IPC分类号： G01R31/28 , G01R31/3185 , H03K19/00 , H03K19/0944 , H03K19/173 , G06F15/20
CPC分类号： G01R31/318536 , H03K19/1738
摘要： Groups of DCVS (Differential Cascode Voltage Switch) circuits are interconnected by single-track data transfer connections. Each group contains one or more DCVS tree circuits, through which data signals propagate only on dual-track connections. In each group, at least one DCVS tree circuit is configured as an input boundary tree, and at least one tree circuit is configured as an output boundary tree. All data inputs externally applied to a group, are transferred only through input boundary trees of the group, and all data outputs transferred out of a group leave the group only through output boundary trees of the group. If a group has only a single tree, that tree serves as input and output boundary tree of the group. Each input boundary tree of each group has one or more associated primary shift register latch (SRL) circuits through which all external data inputs to that tree are transferred. Such external data inputs are received through the single-track connections mentioned above. The primary SRL circuits are also used to present predeterminable test data inputs to respective trees, and to collect primary test data outputs representing signals received through the single-track connections. In such usage, the SRL circuits are connected as a scannable shift register. Each output boundary tree has an exclusive-OR (XOR) circuit for indicating if the respective tree is in a legal or illegal state. The XOR circuits connect to secondary scannable SRL circuits for external presentation of illegal state indication. The primary test data outputs together with the externally presented illegal state indications form a basis for detecting and locating any faulty state in any group.
摘要翻译： DCVS（差分串联电压开关）电路组通过单轨数据传输连接相互连接。每组包含一个或多个DCVS树电路，数据信号仅通过双路连接传播。在每个组中，至少一个DCVS树电路被配置为输入边界树，并且至少一个树电路被配置为输出边界树。外部应用于组的所有数据输入仅通过组的输入边界树进行传输，并且从组中传出的所有数据输出仅通过组的输出边界树离开组。如果一个组只有一棵树，则该树用作该组的输入和输出边界树。每个组的每个输入边界树具有一个或多个相关联的主移位寄存器锁存（SRL）电路，通过该电路，传输该树的所有外部数据输入。这样的外部数据输入通过上述单轨连接来接收。主要的SRL电路还用于向各树提供可预测的测试数据输入，并收集表示通过单轨道连接接收的信号的主要测试数据输出。在这种使用中，SRL电路作为可扫描移位寄存器连接。每个输出边界树具有异或（XOR）电路，用于指示相应的树是否处于合法或非法状态。 XOR电路连接到二次可扫描的SRL电路，用于外部呈现非法状态指示。主要测试数据输出与外部提供的非法状态指示一起构成检测和定位任何组中任何故障状态的基础。

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