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1. 发明授权

US5793094A Methods for fabricating anti-fuse structures 失效
标题翻译：制造抗熔丝结构的方法
公开(公告)号：US5793094A
公开(公告)日：1998-08-11
申请号：US579780
申请日：1995-12-28
申请人： Ivan Sanchez , Yu-Pin Han , Ying-Tsong Loh , Walter D. Parmantie
发明人： Ivan Sanchez , Yu-Pin Han , Ying-Tsong Loh , Walter D. Parmantie
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： A method for substantially reducing variations in a programming voltage of an anti-fuse structure formed on an integrated circuit wafer. The anti-fuse structure has a metal-one layer, an anti-fuse layer disposed above the metal-one layer, a oxide layer disposed above the anti-fuse layer, and a via hole in the oxide layer through to the anti-fuse layer for receiving a deposition of a metal-two material. The method includes the step of rendering a selected anti-fuse area susceptible to fuse link formation by reducing a resistivity of the selected anti-fuse area to diffusion of atoms from one of the metal-one layer and the metal-two layer when a programming voltage is applied between the metal one layer and the metal two layer. The selected anti-fuse area is located in the anti-fuse layer and substantially adjacent to and outside of an anti-fuse area directly below the via hole. The method further includes the step of depositing the metal-two material into the via hole.
摘要翻译：一种用于基本上减少在集成电路晶片上形成的抗熔丝结构的编程电压的变化的方法。反熔丝结构具有金属一层，设置在金属一层上方的抗熔丝层，设置在抗熔融层上方的氧化物层，以及氧化物层中的通孔到反熔丝用于接收金属二材料的沉积的层。该方法包括以下步骤：当编程时，通过降低所选择的反熔丝区域与金属层和金属二层中的一个的原子的扩散，使选择的抗熔丝区域易于熔融链接形成在金属一层和金属两层之间施加电压。所选择的反熔丝区域位于反熔丝层中，并且基本上邻近通孔正下方的反熔丝区域的外部。该方法还包括将金属二材料沉积到通孔中的步骤。

2. 发明授权

US5783467A Method of making antifuse structures using implantation of both neutral and dopant species 失效
标题翻译：使用中性和掺杂物种植物制造反熔丝结构的方法
公开(公告)号：US5783467A
公开(公告)日：1998-07-21
申请号：US582844
申请日：1995-12-29
申请人： Yu-Pin Han , Ying-Tsong Loh , Ivan Sanchez
发明人： Yu-Pin Han , Ying-Tsong Loh , Ivan Sanchez
IPC分类号： H01L21/8246 , H01L27/112 , H01L21/82
CPC分类号： H01L27/11206 , H01L27/112
摘要： An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.
摘要翻译：反熔丝结构包括第一电极，在第一电极上方的增强非晶硅层，以及增强非晶硅层上的第二电极。通过将中性物质和掺杂剂物质的离子注入到非晶硅的沉积层中形成增强非晶硅层，使得反熔丝结构将在编程状态下具有稳定的导电链路，并且使得其将被在非编程状态下较不易于断态泄漏。制造反熔丝结构的方法包括形成下电极，在下电极上沉积非晶硅层，将中性物质和掺杂剂物质离子注入到非晶硅层中，以及在非晶硅层上形成上电极。

3. 发明授权

US5821558A Antifuse structures 失效
标题翻译：防腐结构
公开(公告)号：US5821558A
公开(公告)日：1998-10-13
申请号：US792791
申请日：1997-02-03
申请人： Yu-Pin Han , Ying-Tsong Loh , Ivan Sanchez
发明人： Yu-Pin Han , Ying-Tsong Loh , Ivan Sanchez
IPC分类号： H01L21/8246 , H01L27/112 , H01L29/04 , H01L27/02
CPC分类号： H01L27/11206 , H01L27/112
摘要： An antifuse structure includes a first electrode, a layer of enhanced amorphous silicon over the first electrode, and a second electrode over the layer of enhanced amorphous silicon. The layer of enhanced amorphous silicon is formed by an ion-implantation of a neutral species and a dopant species into a deposited layer of amorphous silicon, such that the antifuse structure will have a stable conductive link in a programmed state and such that it will be less susceptible to off-state leakage in an unprogrammed state. A method for making an antifuse structure includes forming a lower electrode, depositing an amorphous silicon layer over the lower electrode, ion-implanting a neutral species and a dopant species into the amorphous silicon layer, and forming an upper electrode over the amorphous silicon layer.
摘要翻译：反熔丝结构包括第一电极，在第一电极上方的增强非晶硅层，以及增强非晶硅层上的第二电极。通过将中性物质和掺杂剂物质的离子注入到非晶硅的沉积层中形成增强非晶硅层，使得反熔丝结构将在编程状态下具有稳定的导电链路，并且使得其将被在非编程状态下较不易于断态泄漏。制造反熔丝结构的方法包括形成下电极，在下电极上沉积非晶硅层，将中性物质和掺杂剂物质离子注入到非晶硅层中，以及在非晶硅层上形成上电极。

4. 发明授权

US5789795A Methods and apparatus for fabricationg anti-fuse devices 失效
标题翻译：制造反熔丝器件的方法和装置
公开(公告)号：US5789795A
公开(公告)日：1998-08-04
申请号：US579824
申请日：1995-12-28
申请人： Ivan Sanchez , Yu-Pin Han , Miguel A. Delgado , Ying-Tsong Loh
发明人： Ivan Sanchez , Yu-Pin Han , Miguel A. Delgado , Ying-Tsong Loh
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： An integrated circuit having a semiconductor substrate and an anti-fuse structure formed on the semiconductor substrate. The anti-fuse structure includes a metal-one layer and an anti-fuse layer disposed above the metal-one layer. The anti-fuse layer has a first resistance value when the anti-fuse structure is unprogrammed and a second resistance value lower than the first resistance value when the anti-fuse structure is programmed. There is further provided an etch stop layer disposed above the anti-fuse layer, and an inter-metal oxide layer disposed above the etch stop layer with the inter-metal oxide layer has a via formed therein. Additionally, there is further provided a metal-two layer disposed above the inter-metal oxide layer. In this structure, a portion of the metal-two layer is in electrical contact with the anti-fuse layer through the via in the inter-metal oxide layer.
摘要翻译：具有形成在半导体衬底上的半导体衬底和抗熔丝结构的集成电路。反熔丝结构包括金属一层和设置在金属一层上方的抗熔丝层。当抗熔丝结构未被编程时，抗熔丝层具有第一电阻值，并且当编程防熔丝结构时，抗熔丝层具有低于第一电阻值的第二电阻值。还提供了设置在反熔丝层上方的蚀刻停止层，并且设置在蚀刻停止层上方的金属间氧化物层与金属间氧化物层在其中形成通孔。此外，还提供了设置在金属间氧化物层上方的金属二层。在该结构中，金属二层的一部分通过金属间氧化物层中的通孔与抗熔融层电接触。

5. 发明授权

US5753540A Apparatus and method for programming antifuse structures 失效
标题翻译：用于编程反熔丝结构的装置和方法
公开(公告)号：US5753540A
公开(公告)日：1998-05-19
申请号：US699867
申请日：1996-08-20
申请人： Koucheng Wu , Ivan Sanchez , Yu-Pin Han , Ying-Tsong Loh
发明人： Koucheng Wu , Ivan Sanchez , Yu-Pin Han , Ying-Tsong Loh
IPC分类号： H01L23/525 , H01L21/82
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011
摘要： Disclosed is a method for programming an antifuse structure. The antifuse structure is programmed by applying an alternating current having alternating current pulses between a bottom and a top electrode to generate a conduction path through an antifuse material sandwiched between the electrodes. The conduction path is formed incrementally due to an electron flow produced as a result of each alternating current pulse thereby defining the conduction path at a substantially centered portion of the antifuse material.
摘要翻译：公开了一种用于编程反熔丝结构的方法。反熔丝结构通过在底部和顶部电极之间施加具有交流电脉冲的交流电来编程，以产生穿过夹在电极之间的反熔丝的导电路径。由于由于每个交流脉冲而产生的电子流，传导路径增量地形成，从而在反熔丝材料的基本中心部分处限定导电路径。

6. 发明授权

US06444502B1 Method for forming strapless anti-fuse structure 失效
标题翻译：形成无肩带反熔丝结构的方法
公开(公告)号：US06444502B1
公开(公告)日：2002-09-03
申请号：US09006926
申请日：1998-01-14
申请人： Ivan Sanchez , Danny Echtle , Landon B. Vines
发明人： Ivan Sanchez , Danny Echtle , Landon B. Vines
IPC分类号： H01L2182
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure and method for forming such structure. In one embodiment, the anti-fuse structure of the present invention includes a dielectric layer which is deposited over a metal layer. The semiconductor substrate is then masked and etched so as to form openings in the dielectric layer. Metal is deposited over the semiconductor substrate and is polished so as to remove the metal which overlies the dielectric layer so as to form a plug which extends through the dielectric layer and which electrically connects to the metal layer. An amorphous silicon block is then deposited, masked and etched so as to form an amorphous silicon block over the plug. A metal layer is then deposited, masked and etched so as to form an interconnect. The amorphous silicon block lies between the metal layer and the interconnect so as to prevent the flow of electrical current until such time as the anti-fuse is activated. The anti-fuse is activated by running a voltage higher than the threshold voltage of the anti-fuse between the interconnect and the plug. Upon activation of the anti-fuse, an electrical connection is made between the interconnect and the metal layer.
摘要翻译：一种用于形成这种结构的抗熔丝结构和方法。在一个实施例中，本发明的抗熔丝结构包括沉积在金属层上的电介质层。然后对半导体衬底进行掩模蚀刻，以在电介质层中形成开口。金属沉积在半导体衬底上并被抛光，以去除覆盖在电介质层上的金属，从而形成延伸穿过电介质层并与金属层电连接的插塞。然后沉积，掩蔽和蚀刻非晶硅块，以在塞上形成非晶硅块。然后沉积，掩蔽和蚀刻金属层以形成互连。非晶硅块位于金属层和互连之间，以防止电流的流动，直到反熔丝被激活为止。通过运行高于互连和插头之间的反熔丝的阈值电压的电压来激活反熔丝。在激活抗熔丝时，在互连和金属层之间形成电连接。

7. 发明授权

US6156588A Method of forming anti-fuse structure 失效
标题翻译：形成抗熔丝结构的方法
公开(公告)号：US6156588A
公开(公告)日：2000-12-05
申请号：US102367
申请日：1998-06-23
申请人： Ivan Sanchez , Miguel A. Delgado
发明人： Ivan Sanchez , Miguel A. Delgado
IPC分类号： H01L23/525 , H01L21/82
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： The invention relates generally to integrated circuits and, in particular, to methods of forming anti-fuse structures during integrated circuit manufacture. In an exemplary embodiment of the invention, a conductive base layer is formed over a semiconductor substrate. An insulating layer is formed on the conductive base layer and is patterned to expose a portion of the conductive base layer. An anti-fuse layer is formed on the insulating layer and the exposed portion of the conductive base layer. A conductive protection layer is formed on the anti-fuse layer. An anti-fuse island is formed by sequentially removing a portion of the conductive protection layer, and underlying portions of the anti-fuse layer and the insulating layer. The conductive base layer is patterned after forming the anti-fuse island. The invention provides a simplified method for the formation of anti-fuse structures which is compatible with submicron device geometries.
摘要翻译：本发明一般涉及集成电路，尤其涉及在集成电路制造期间形成抗熔丝结构的方法。在本发明的示例性实施例中，在半导体衬底上形成导电基层。在导电基底层上形成绝缘层，并将其图形化以暴露导电基底层的一部分。在绝缘层和导电性基底层的露出部分上形成反熔丝层。在反熔丝层上形成导电保护层。通过依次去除导电保护层的一部分以及反熔丝层和绝缘层的下面部分，形成反熔丝岛。在形成抗熔丝岛之后，导电基底层被图案化。本发明提供了形成与亚微米器件几何相容的抗熔丝结构的简化方法。

8. 发明授权

US6016001A Metal to amorphous silicon to metal anti-fuse structure 失效
标题翻译：金属到非晶硅到金属反熔丝结构
公开(公告)号：US6016001A
公开(公告)日：2000-01-18
申请号：US878707
申请日：1997-06-19
申请人： Ivan Sanchez , Danny Echtle , Landon B. Vines
发明人： Ivan Sanchez , Danny Echtle , Landon B. Vines
IPC分类号： H01L23/525 , H01L29/94
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： An anti-fuse structure and method for forming such structure. In one embodiment, the anti-fuse structure of the present invention includes a dielectric layer which is deposited over a metal layer. The semiconductor substrate is then masked and etched so as to form openings in the dielectric layer. Metal is deposited over the semiconductor substrate and is polished so as to remove the metal which overlies the dielectric layer so as to form a plug which extends through the dielectric layer and which electrically connects to the metal layer. An amorphous silicon block is then deposited, masked and etched so as to form an amorphous silicon block over the plug. A metal layer is then deposited, masked and etched so as to form an interconnect. The amorphous silicon block lies between the metal layer and the interconnect so as to prevent the flow of electrical current until such time as the anti-fuse is activated. The anti-fuse is activated by running a voltage higher than the threshold voltage of the anti-fuse between the interconnect and the plug. Upon activation of the anti-fuse, an electrical connection is made between the interconnect and the metal layer.
摘要翻译：一种用于形成这种结构的抗熔丝结构和方法。在一个实施例中，本发明的抗熔丝结构包括沉积在金属层上的电介质层。然后对半导体衬底进行掩模蚀刻，以在电介质层中形成开口。金属沉积在半导体衬底上并被抛光，以去除覆盖在电介质层上的金属，从而形成延伸穿过电介质层并与金属层电连接的插塞。然后沉积，掩蔽和蚀刻非晶硅块，以在塞上形成非晶硅块。然后沉积，掩蔽和蚀刻金属层以形成互连。非晶硅块位于金属层和互连之间，以防止电流的流动，直到反熔丝被激活为止。通过运行高于互连和插头之间的反熔丝的阈值电压的电压来激活反熔丝。在激活抗熔丝时，在互连和金属层之间形成电连接。

9. 发明授权

US5899707A Method for making doped antifuse structures 失效
标题翻译：制造掺杂反熔丝结构的方法
公开(公告)号：US5899707A
公开(公告)日：1999-05-04
申请号：US699866
申请日：1996-08-20
申请人： Ivan Sanchez , Landon B. Vines
发明人： Ivan Sanchez , Landon B. Vines
IPC分类号： H01L23/525 , H01L21/82
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： An antifuse structure and method for making the antifuse structure having a doped antifuse layer is disclosed. The doped antifuse layer is preferably deposited over a lower electrode. A barrier layer may then be formed over the doped antifuse layer and an upper electrode may subsequently be deposited over the barrier layer. The method of depositing the doped antifuse layer includes: (a) providing a chemical vapor deposition reactor having a support chuck for supporting a partially fabricated silicon wafer; (b) powering up the chemical vapor deposition reactor and heating the partially fabricated silicon wafer; (c) selecting a dopant species for the antifuse layer (e.g, n-type or p-type); (d) introducing a gaseous mixture of a silane compound and the selected dopant species into the chemical vapor deposition reactor with the aid of a neutral species; and (e) depositing the antifuse layer over the lower electrode. When the antifuse structure is programmed, a wider conduction path is formed in the doped antifuse layer and deprogrammed states are prevented.
摘要翻译：公开了一种用于制造具有掺杂反熔丝层的反熔丝结构的反熔丝结构和方法。掺杂的反熔丝层优选沉积在下电极上。然后可以在掺杂的反熔丝层上形成阻挡层，并且随后可以在阻挡层上沉积上电极。沉积掺杂反熔丝层的方法包括：（a）提供具有用于支撑部分制造的硅晶片的支撑卡盘的化学气相沉积反应器; （b）加电化学气相沉积反应器并加热部分制造的硅晶片; （c）选择反熔丝层的掺杂物种（例如，n型或p型）; （d）借助于中性物质将硅烷化合物和所选掺杂剂物质的气体混合物引入化学气相沉积反应器; 和（e）将反熔丝层沉积在下电极上。当反熔丝结构被编程时，在掺杂反熔丝层中形成更宽的传导路径，并且防止了解编程状态。

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