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1. 发明专利

JP2000195860A METHOD OF INCREASING ELECTROMIGRATION LIFETIME IN METAL INTERCONNECT 失效
公开(公告)号：JP2000195860A
公开(公告)日：2000-07-14
申请号：JP37512499
申请日：1999-12-28
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： SCHNABEL RAINER FLORIAN , RONALD PHILLIPI , HOINKIS MARK , WEBER STEFAN , ROY IGARUDEN , WEIGAND PETER , LAWRENCE CLEVENGER
IPC分类号： H01L23/52 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/82
摘要： PROBLEM TO BE SOLVED: To increase the electromigration lifetime of a semiconductor device by stacking a liner by an ionizing metal plasma physical deposition method, thereby reducing the mass carriage by electromigration. SOLUTION: A dielectric layer is made on a substrate. The dielectric layer is patterned, and a contact hole 26 is made, and conductive material is stacked on a dielectric layer so as to fill the contact hole 26 and cover the dielectric layer. Next, excess material is removed by polishing from the surface 29 so as to make a flat surface for an additional layer. Next, a liner 40 is stacked on the dielectric layer 29. This liner consists of a material having high electromigration resistance. For example, titanium(Ti) and its alloy tantalum(Ta) and its alloy, or TiN or Tan is included as such a liner material. This liner 40 is stacked, using an ionizing metal plasma physical deposition method.

2. 发明申请

WO0199160A3 REDUCTION OF TOPOGRAPHY BETWEEN SUPPORT REGIONS AND ARRAY REGIONS OF MEMORY DEVICES 审中-公开
标题翻译：支持区域和阵列区域之间的地理位置减少
公开(公告)号：WO0199160A3
公开(公告)日：2002-10-17
申请号：PCT/US0119684
申请日：2001-06-20
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： SCHNABEL RAINER FLORIAN , RADENS CARL J , LANDIS HOWARD , PARK YOUNG JIN , KOTECKI DAVID , REITH ARMIN M , TRICKLE WAYNE , WORDEMAN MATTHEW R
IPC分类号： H01L27/108
CPC分类号： H01L27/10805 , H01L27/10808
摘要： A semiconductor memory device (100), in accordance with the present invention, includes a substrate having a major surface including an array region (102) and a support region (104). The array region includes memory cell structures (106) having a first height above the major surface of the substrate. The support area includes dummy structures (119) formed therein having a second height above the major surface. A dielectric layer (118) is formed over the memory cell structures in the array region and the dummy structures in the support region such that a top surface (122) of the dielectric layer is substantially planar wherein topographical features are substantially eliminated on the dielectric layer across the array region and the support region.
摘要翻译：根据本发明的半导体存储器件（100）包括具有包括阵列区域（102）和支撑区域（104）的主表面的衬底。阵列区域包括在衬底的主表面上方具有第一高度的存储单元结构（106）。支撑区域包括形成在其中的在主表面上方具有第二高度的虚拟结构（119）。在阵列区域中的存储单元结构和支撑区域中的虚拟结构之间形成电介质层（118），使得电介质层的顶表面（122）基本上是平面的，其中在介电层上基本上消除了形貌特征跨越阵列区域和支撑区域。

3. 发明申请

WO0126139A3 DRAM BIT LINES AND SUPPORT CIRCUITRY CONTACTING SCHEME 审中-公开
标题翻译： DRAM位线和支持电路联系方案
公开(公告)号：WO0126139A3
公开(公告)日：2001-10-18
申请号：PCT/US0027216
申请日：2000-10-02
申请人： INFINEON TECHNOLOGIES CORP
发明人： SCHNABEL RAINER FLORIAN , GRUENING ULRIKE , RUPP THOMAS , MUELLER GERHARD
IPC分类号： G11C5/06 , G11C7/18 , G11C11/4097 , H01L21/285 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10885 , G11C5/063 , G11C7/18 , G11C11/4097 , H01L21/28525 , H01L21/76807 , H01L21/76897 , H01L27/105 , H01L27/10888 , H01L27/10894
摘要： A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels, in accordance with the present invention, includes forming gate structures (204) for transistors in an array region (212) and a support region (214) of a substrate (202). First contacts (222) are formed down to diffusion regions between the gate structures in the array region. The first contacts have a height which is substantially the same for all first contacts in the array region. Second contacts (232) are formed between first level bitlines (234) in the array region and a first portion of the first contacts, while forming second contacts (236 and 260) to a first metal layer (233, 264) from the gate structures (204) and diffusion regions (262) in the support region. Third contacts (246) are formed between second level bitlines in the array region and a second portion of the first contacts, while forming third contacts to a second metal layer (251, 268) from the first metal layer in the support region.
摘要翻译：根据本发明，制造具有由三个接触电平构成的分裂电平折叠位线结构的半导体存储器的方法包括：在阵列区域（212）和支撑区域（214）中形成用于晶体管的栅极结构（204）的衬底（202）。第一触点（222）形成在阵列区域中的栅极结构之间的扩散区域。第一触点具有与阵列区域中的所有第一触点基本相同的高度。第二触点（232）形成在阵列区域中的第一级位线（234）和第一触点的第一部分之间，同时从栅极结构形成第二触点（236和260）到第一金属层（233,264）（204）和扩散区（262）。第三触点（246）形成在阵列区域中的第二电平位线和第一触点的第二部分之间，同时从支撑区域中的第一金属层形成第三触点到第二金属层（251,268）。

4. 发明专利

JP2002016070A MULTILAYER MICROELECTRONIC DEVICE AND ITS FORMING METHOD 失效
公开(公告)号：JP2002016070A
公开(公告)日：2002-01-18
申请号：JP2001171050
申请日：2001-06-06
申请人： IBM
发明人： LAWRENCE ALFRED CLEVENGER , RONALD JEAN PHILIPPI , RODBELL KENNETH PARKER , ROY CHARLES IGGULDEN , CHAOKUN FUU , LINN MARIE GIGNAC , WEBER STEPHAN , GAMBINO JEFFREY PETER , SCHNABEL RAINER FLORIAN
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532
摘要： PROBLEM TO BE SOLVED: To provide a dual damascene process that can reliably form aluminum interconnection exhibiting improved electro migration characteristics, as compared with aluminum interconnection that is formed by the conventional RIE technique. SOLUTION: More specifically, the dual damascene process depends on a PVD-Ti/CVD-TiN barrier layer and forms an aluminum line showing great reduction in a saturation resistance level, the inhibition of the electro migration, or both of them especially in a line longer than 100 micrometers. The electromigration life time of the dual damascene aluminum line depends greatly on the conditions of materials and material-filling processes. When there is deviation in the materials and treatment, the electromigration life time way possibly become shorter than life time that is achieved by an aluminum RIE interconnection line, and this becomes a serious matter.

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