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1. 发明专利

JP2010251459A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2010251459A
公开(公告)日：2010-11-04
申请号：JP2009098072
申请日：2009-04-14
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ISHIGAKI TAKASHI , TSUCHIYA RYUTA , MORITA YUSUKE , SUGII NOBUYUKI
IPC分类号： H01L29/786 , H01L29/41
CPC分类号： H01L29/785 , H01L29/66795
摘要： PROBLEM TO BE SOLVED: To improve characteristics of a semiconductor device with a FINFET. SOLUTION: The FINFET has: a channel layer 3 arranged in an arch shape on a silicon substrate 1 and made of monocrystalline silicon; a front gate electrode EG1 formed on a part of an outside of the channel layer 3 through a front gate insulating film IG1; and a back gate electrode EG2 formed so as to be buried inside the channel layer through a back gate insulating film IG2. The back gate electrode EG2 arranged inside the arch shape is arranged so as to pass through the front gate electrode EG1. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提高具有FINFET的半导体器件的特性。解决方案：FINFET具有：在硅衬底1上以拱形形式布置并由单晶硅制成的沟道层3; 通过前栅极绝缘膜IG1形成在沟道层3的外部的一部分上的前栅电极EG1; 以及形成为通过背栅绝缘膜IG2埋设在沟道层内的背栅电极EG2。布置在拱形内侧的背栅电极EG2被布置成穿过前栅电极EG1。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2013098284A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2013098284A
公开(公告)日：2013-05-20
申请号：JP2011238406
申请日：2011-10-31
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ISHIGAKI TAKASHI , TSUCHIYA RYUTA , MOCHIZUKI KAZUHIRO , TERANO AKIHISA
IPC分类号： H01L21/337 , H01L21/28 , H01L21/336 , H01L21/338 , H01L29/423 , H01L29/49 , H01L29/778 , H01L29/78 , H01L29/808 , H01L29/812
CPC分类号： H01L29/4236 , H01L29/155 , H01L29/2003 , H01L29/402 , H01L29/42376 , H01L29/66462 , H01L29/7787
摘要： PROBLEM TO BE SOLVED: To provide a technique that achieves normally-off and low on-resistance in a nitride semiconductor device having a plurality of channels.SOLUTION: A semiconductor device includes: a nitride semiconductor stack 10 having at least two heterozygotes in which first nitride semiconductor layers 3, 5, and 7 and second nitride semiconductor layers 4, 6, and 8 having a larger forbidden band width than the first nitride semiconductor layers are stacked; a drain electrode 14 and a source electrode 13 provided on the nitride semiconductor stack 10; and gate electrodes provided facing both the drain electrode 14 and the source electrode 13. The drain electrode 14 and the source electrode 13 are disposed on a surface or side surfaces of the nitride semiconductor stack 10. The gate electrodes have a first gate electrode 15 provided in the depth direction of the nitride semiconductor stack 10 and a second gate electrode 16 having a different depth in the depth direction of the nitride semiconductor stack 10 from the first gate electrode 15.
摘要翻译：要解决的问题：提供一种在具有多个通道的氮化物半导体器件中实现常闭和低导通电阻的技术。解决方案：半导体器件包括：氮化物半导体堆叠10，其具有至少两个杂合子，其中第一氮化物半导体层3,5和7以及具有较大禁带宽度的第二氮化物半导体层4,6和8比堆叠第一氮化物半导体层; 设置在氮化物半导体堆叠10上的漏电极14和源电极13; 以及设置在漏极电极14和源电极13两端的栅电极。漏电极14和源电极13设置在氮化物半导体堆叠10的表面或侧表面上。栅电极具有第一栅电极15，在氮化物半导体堆叠10的深度方向上和在氮化物半导体堆叠10的深度方向上与第一栅电极15具有不同深度的第二栅电极16.版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2010251366A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010251366A
公开(公告)日：2010-11-04
申请号：JP2009096015
申请日：2009-04-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SUGII NOBUYUKI , TSUCHIYA RYUTA , KIMURA SHINICHIRO , ISHIGAKI TAKASHI , MORITA YUSUKE , YOSHIMOTO HIROYUKI
IPC分类号： H01L29/786 , H01L21/76 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/76283
摘要： PROBLEM TO BE SOLVED: To provide a technique for achieving low power consumption of a semiconductor device by improving a shape at a boundary between an SOI layer of an SOI substrate and shallow-trench element isolation.
SOLUTION: A position (SOI edge 10) at which a main surface of a silicon substrate 3 and a line extending along a side surface of an SOI layer 1 intersect with each other is retreated in a direction opposite to shallow-trench element isolation 4 compared to a position (STI edge 9) at which a line extending along a sidewall 8 of a shallow trench and a line extending along the main surface of the silicon substrate 3 intersect with each other. A corner of the silicon substrate 3 at the STI edge 9 has a curved surface.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过改善SOI衬底的SOI层和浅沟槽元件隔离之间的边界处的形状来实现半导体器件的低功耗的技术。解决方案：硅衬底3的主表面和沿着SOI层1的侧表面延伸的线彼此相交的位置（SOI边缘10）在与浅沟槽元件相反的方向上退避隔离4与沿着浅沟槽的侧壁8延伸的线和沿着硅衬底3的主表面延伸的线相交的位置（STI边缘9）相比。硅衬底3在STI边缘9处的角部具有弯曲表面。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2013251494A Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013251494A
公开(公告)日：2013-12-12
申请号：JP2012127131
申请日：2012-06-04
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ISHIGAKI TAKASHI , TSUCHIYA RYUTA
IPC分类号： H01L29/78 , H01L29/12
摘要： PROBLEM TO BE SOLVED: To provide a technique capable of improving performance of a semiconductor device.SOLUTION: A vertical MISFET50 comprises an ntype SiC substrate 10 in which a drain electrode 11 is formed on a lower surface thereof and an ntype epitaxial layer 12 is formed on an upper surface thereof. A P type body region 13 is formed in an upper layer part of the ntype epitaxial layer 12, and an ntype source region 14 and a ptype body contact region 15 are formed in an upper layer part of the p type body region 13. A first gate electrode 19 is formed on an upper surface of the portion sandwiched between the ntype source region 14 and the ntype epitaxial layer 12 in the p type body region 13 via a first gate insulating film 18. A second gate electrode 22 is formed on an upper surface of the ptype body contact region 15.
摘要翻译：要解决的问题：提供能够提高半导体器件的性能的技术。解决方案：垂直MISFET50包括n型SiC衬底10，其中在其下表面上形成漏电极11，并形成n型外延层12 在其上表面。 AP型体区域13形成在n型外延层12的上层部分中，并且在p型体区域13的上层部分中形成n型源极区域14和p型体接触区域15.第一栅极电极19经由第一栅极绝缘膜18形成在p型体区13中夹在n型源极区14和n型外延层12之间的部分的上表面上。第二栅电极22形成在上表面的P型体接触区域15。

5. 发明专利

JP2013098226A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2013098226A
公开(公告)日：2013-05-20
申请号：JP2011237242
申请日：2011-10-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MOCHIZUKI KAZUHIRO , ISHIGAKI TAKASHI , TSUCHIYA RYUTA , KAMESHIRO NORIFUMI
IPC分类号： H01L29/47 , H01L29/861 , H01L29/868 , H01L29/872
CPC分类号： H01L29/872
摘要： PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device by preventing an occurrence of a reverse current leakage when crystal defect is generated in a drift layer of a Schottky interface of a Schottky diode using a substrate containing SiC.SOLUTION: In a Schottky diode including a Schottky junction part of a drift layer 2 on a semiconductor substrate and a Schottky electrode 4, an acceptor impurity is introduced on a top face of crystal defect 12 reaching a top face of the drift layer 2 with a concentration and at a depth which are defined depending on a metal composing the Schottky electrode 4 to form a p-type semiconductor region 3 thereby to prevent increase in reverse leakage current.
摘要翻译：要解决的问题：为了通过在使用含有SiC的基板的肖特基二极管的肖特基二极管的漂移层中产生晶体缺陷时防止发生反向电流泄漏来提高半导体器件的可靠性。解决方案：在包括半导体衬底上的漂移层2的肖特基结部分和肖特基电极4的肖特基二极管中，受主杂质被引入晶体缺陷12的顶面，到达漂移层的顶面 2，其浓度和深度根据构成肖特基电极4的金属限定，以形成p型半导体区域3，从而防止反向漏电流的增加。版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2012099509A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012099509A
公开(公告)日：2012-05-24
申请号：JP2009008851
申请日：2009-01-19
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YOSHIMOTO HIROYUKI , SUGII NOBUYUKI , TSUCHIYA RYUTA , ISHIGAKI TAKASHI , MORITA YUSUKE
IPC分类号： H01L29/786 , H01L21/336 , H01L21/822 , H01L27/04 , H03K19/20
CPC分类号： H01L21/28282 , G11C16/0466 , H01L21/326 , H01L29/4234 , H01L29/513 , H01L29/78603
摘要： PROBLEM TO BE SOLVED: To provide a technique capable of controlling a threshold voltage and improving a reliability of a semiconductor device without enlarging a circuit area after a LSI of a field effect transistor is manufactured.SOLUTION: The field effect semiconductor device comprises a laminated layer (a first silicon oxide film 2 having a thickness of 3 nm to 4 nm, a silicon nitride film 3 having a thickness of 0.3 nm to 2 nm, a second silicon oxide film 4 having a thickness of 5 nm to 10 nm, a SOI layer 5 having a thickness of 3 nm to 20 nm) provided on an upper surface of a silicon semiconductor supporting substrate 1; source/drain diffusion layers 6 provided mutually oppositely via a predetermined gap on the structure; a gate insulating film 7 formed on a surface of the semiconductor substrate between the source diffusion layer and the drain diffusion layer; and a gate electrode 8 formed on the gate insulating film. By applying a voltage from the silicon supporting substrate 1, charges are kept in the silicon nitride film 3 in a certain time due to a direct tunnel effect, to control the threshold voltage.
摘要翻译：要解决的问题：提供一种能够在制造场效应晶体管的LSI之后，在不扩大电路面积的情况下，能够控制阈值电压并提高半导体器件的可靠性的技术。解决方案：场效应半导体器件包括层叠层（厚度为3nm至4nm的第一氧化硅膜2，厚度为0.3nm至2nm的氮化硅膜3，第二氧化硅设置在硅半导体支撑衬底1的上表面上，厚度为5nm至10nm的膜4，厚度为3nm至20nm的SOI层5; 源极/漏极扩散层6经由该结构上的预定间隙相互相对设置; 在源极扩散层和漏极扩散层之间形成在半导体衬底的表面上的栅极绝缘膜7; 以及形成在栅极绝缘膜上的栅电极8。通过从硅支撑基板1施加电压，由于直接隧道效应，在一定时间内将电荷保持在氮化硅膜3中，以控制阈值电压。版权所有（C）2012，JPO＆INPIT

7. 发明专利

JP2012043864A Semiconductor device and method of manufacturing the semiconductor device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2012043864A
公开(公告)日：2012-03-01
申请号：JP2010181822
申请日：2010-08-16
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MOCHIZUKI KAZUHIRO , SHIMAMOTO YASUHIRO , ISHIGAKI TAKASHI , TERANO AKIHISA , TSUCHIYA TOMONOBU
IPC分类号： H01L29/47 , H01L29/872
CPC分类号： H01L29/872 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/66143
摘要： PROBLEM TO BE SOLVED: To improve characteristics of a semiconductor device and a Schottky barrier diode.SOLUTION: A semiconductor device comprises: stacks H including at least one hetero junction in which a first film and a second film having different forbidden band widths are stacked; a dummy stack D composed of the same layers as the stacks H; trenches G provided between the stacks H and the dummy stack D; a first electrode SE that is disposed so as to extend from the upper portion of the stacks H to the upper portion of the dummy stack D, including the inside of the trenches, is disposed so as to contact first sidewalls of the stacks H, and is Schottky-connected to the stacks H; and second electrodes OHE disposed so as to contact second sidewalls opposed to the first sidewalls of the stacks H. The fabrication of the sidewall contacts by remaining the dummy stack D, providing the trenches G between the stacks H, and the first electrode SE filled in the trenches can reduce the probability of the occurrence of defects in the bottoms of the trenches during etching of the stacks H, thereby reducing reverse leakage current.
摘要翻译：要解决的问题：提高半导体器件和肖特基势垒二极管的特性。解决方案：半导体器件包括：堆叠H，其包括至少一个异质结，其中第一膜和具有不同禁带宽度的第二膜被堆叠; 由与层叠体H相同的层构成的虚拟堆栈D; 设置在堆叠H和虚设堆叠D之间的沟槽G; 设置成从堆叠H的上部延伸到包括沟槽内部的虚设堆叠D的上部的第一电极SE设置成接触堆叠H的第一侧壁，并且肖特基连接到堆栈H; 以及第二电极OHE，其设置成接触与堆叠H的第一侧壁相对的第二侧壁。通过保留虚设堆叠D，提供堆叠H之间的沟槽G和填充的第一电极SE，制造侧壁接触在蚀刻堆叠H期间，沟槽可以降低沟槽底部出现缺陷的可能性，从而减少反向漏电流。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP2014041693A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2014041693A
公开(公告)日：2014-03-06
申请号：JP2013242375
申请日：2013-11-22
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： KAWAHARA TAKAYUKI , TAKEMURA RIICHIRO , ISHIGAKI TAKASHI , ITO KIYOO
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L29/82 , H01L43/08
CPC分类号： H01L27/228 , G11C7/1006 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1697 , G11C11/5607
摘要： PROBLEM TO BE SOLVED: To realize various kinds of writing and reading by using a spin injection magnetization reversal type magnetic resistance change element (TMR element).SOLUTION: A first current of a value not less than that of an element which requires a maximum current to reverse its magnetization is fed to a memory cell having a plurality of TMR elements in a direction to reverse its magnetization to either a parallel state or anti-parallel state. Then, a second current of a value necessary to reverse a magnetic resistance state of at least a TMR element except the TMR element requiring the maximum current among the plurality of TMR elements is fed to each of the TMR elements in a direction opposite to the first current, so that multi value writing is carried out.
摘要翻译：要解决的问题：通过使用自旋注入磁化反转型磁阻变化元件（TMR元件）来实现各种写入和读取。解决方案：不小于需要最大电流的元件的值的第一电流反向磁化被馈送到具有多个TMR元件的存储单元，该存储单元沿着将其磁化反转到平行状态或反平行状态的方向。然后，在多个TMR元件中，除了需要最大电流的TMR元件之外的至少TMR元件的磁阻状态反转所需的值的第二电流，以与第一电流，从而进行多值写入。

9. 发明专利

JP2012186331A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012186331A
公开(公告)日：2012-09-27
申请号：JP2011048728
申请日：2011-03-07
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MOCHIZUKI KAZUHIRO , ISHIGAKI TAKASHI , TERANO AKIHISA , TSUCHIYA TOMONOBU
IPC分类号： H01L29/872 , H01L29/47
CPC分类号： H01L29/872 , H01L29/0649 , H01L29/2003 , H01L29/205 , H01L29/66143
摘要： PROBLEM TO BE SOLVED: To reduce reverse leakage current in a Schottky barrier diode.SOLUTION: A semiconductor device comprises: a laminate 6 having a heterojunction 5a, 5b formed from alternately laminating GaN films 3a, 3b and barrier films 4a, 4b, which have forbidden bandwidths different from each other, one on top of another; a first electrode 8 Schottky connected with one sidewall of the laminate 6; and a second electrode 10 formed to contact another sidewall. An oxide film 12 is provided between the first electrode 8 and the barrier films 4a, 4b. Accordingly, reverse leakage current is prevented from flowing via a defect remaining in the barrier films 4a, 4b caused by fabrication of the barrier films 4a, 4b.
摘要翻译：要解决的问题：减少肖特基势垒二极管中的反向泄漏电流。解决方案：半导体器件包括：层叠体6，其具有异质结5a，5b，其彼此之间交替层叠具有彼此不同的带宽的GaN膜3a，3b和阻挡膜4a，4b; 与层叠体6的一个侧壁连接的第一电极8肖特基; 以及形成为接触另一个侧壁的第二电极10。在第一电极8和阻挡膜4a，4b之间设置有氧化膜12。因此，通过阻挡膜4a，4b的制造而导致的阻挡膜4a，4b中残留的缺陷，防止反向泄漏电流流动。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2012186239A Nitride semiconductor diode 有权
标题翻译：氮化物半导体二极管
公开(公告)号：JP2012186239A
公开(公告)日：2012-09-27
申请号：JP2011047107
申请日：2011-03-04
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TERANO AKIHISA , MOCHIZUKI KAZUHIRO , ISHIGAKI TAKASHI
IPC分类号： H01L29/872 , H01L29/47
CPC分类号： H01L29/872 , H01L29/0649 , H01L29/2003
摘要： PROBLEM TO BE SOLVED: To provide a nitride semiconductor diode having lower element resistance and higher forward current as compared with a conventional one, while having a chip area equal to that of the conventional one.SOLUTION: In a Schottky electrode formation region on a nitride semiconductor, the total length of a borderline where a Schottky electrode is in contact with a surface of a nitride semiconductor layer is formed to be longer than the outer periphery length of the Schottky electrode formation region. The total length is preferably 10 times longer than the outer periphery length. For example, the problem can be solved by forming the Schottky electrode in a concentric annular shape.
摘要翻译：要解决的问题：与现有技术相比，提供一种具有较低元件电阻和较高正向电流的氮化物半导体二极管，同时芯片面积与常规芯片面积相同。解决方案：在氮化物半导体上的肖特基电极形成区域中，肖特基电极与氮化物半导体层的表面接触的边界线的总长度形成为比肖特基的外周长度长电极形成区域。总长度优选比外周长度长10倍。例如，可以通过将肖特基电极形成为同心圆形形状来解决问题。版权所有（C）2012，JPO＆INPIT

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