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1. 发明授权

US07886085B2 Removable memory device, phase synchronizing method, phase synchronizing program, medium recording the same, and host terminal 有权
标题翻译：可移动存储设备，相位同步方法，相位同步程序，介质记录和主机终端
公开(公告)号：US07886085B2
公开(公告)日：2011-02-08
申请号：US12295051
申请日：2007-02-20
申请人： Hiroshi Suenaga , Osamu Shibata , Noriaki Takeda , Toru Iwata , Takaharu Yoshida , Yoshiyuki Saito
发明人： Hiroshi Suenaga , Osamu Shibata , Noriaki Takeda , Toru Iwata , Takaharu Yoshida , Yoshiyuki Saito
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： H04L7/10 , G06F1/12 , H04L7/0008 , H04L7/033 , H04L7/044 , H04L7/046
摘要： An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time. A removable memory device that transmits/receives data to and from a host terminal, which includes: a clock reception section that receives a transmission/reception clock, which is used for transmitting/receiving data between the host terminal and the removable memory device, from the host terminal; a phase synchronization pattern generation section that generates a phase synchronization pattern, which is for adjusting a phase of internal reception clock which the host terminal incorporates for receiving data from the removable memory device, based on the transmission/reception clock; and a transmission section that transmits the generated phase synchronization pattern to the host terminal, and in which the phase synchronization pattern includes a first level signal which lasts for at least two cycles, and a second level signal which follows the first level signal and lasts for one cycle, is provided.
摘要翻译：本发明的目的是提供一种提高数据传输效率的技术，其允许同时正确地接收数据。一种向主机终端发送/接收数据的可移动存储装置，包括：接收用于在主机终端和可移动存储装置之间发送/接收数据的发送/接收时钟的时钟接收部分，主机终端; 相位同步模式生成部，其基于所述发送接收时钟生成相位同步模式，所述相位同步模式用于调整所述主机终端结合的用于从所述可移动存储装置接收数据的内部接收时钟的相位; 以及发送部，其将所生成的相位同步模式发送到所述主机终端，并且所述相位同步模式包括持续至少两个周期的第一电平信号，以及在所述第一电平信号之后持续的第二电平信号，提供一个循环。

2. 发明申请

US20090290582A1 SIGNAL TRANSMISSION METHOD, TRANSMISSION/RECEPTION DEVICE, AND COMMUNICATION SYSTEM 有权
标题翻译：信号传输方法，传输/接收设备和通信系统
公开(公告)号：US20090290582A1
公开(公告)日：2009-11-26
申请号：US12295407
申请日：2007-02-20
申请人： Hiroshi Suenaga. , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Noriaki Takeda , Takaharu Yoshida
发明人： Hiroshi Suenaga. , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Noriaki Takeda , Takaharu Yoshida
IPC分类号： H04L12/56 , H04J3/00
CPC分类号： H04L25/14
摘要： It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal. The invention provides a signal transmission method that is characterized in that a reception side and a transmission side partition data into a plurality of data fragments and send and receive the plurality of data fragments over at least two transmission lines, in that the transmission side transmits first data fragments of the plurality of data fragments over a first transmission line of the transmission lines, transmits data packets that include header information, a second data fragment that has the same bit length as the first data fragments, and footer information over a second transmission line other than the first transmission line, and transmits the first data fragments and the second data fragments in synchronization, and in that an interrupt signal for controlling the transmission side is transmitted from the reception side to the transmission side in a time slot that is an interval between first data fragments that are adjacent on the first transmission line.
摘要翻译：本发明的一个目的是抑制由于中断信号的传输引起的数据传输效率的下降。本发明提供了一种信号传输方法，其特征在于，接收侧和发送侧将数据划分成多个数据片段，并通过至少两条传输线发送和接收多个数据片段，其中发送侧首先发送在传输线的第一传输线上的多个数据片段的数据片段，通过第二传输线传输包括标题信息的数据包，具有与第一数据片段相同的位长的第二数据片段，以及页脚信息除了第一传输线之外，并且同步地发送第一数据片段和第二数据片段，并且用于控制发送侧的中断信号在作为间隔的时隙中的从接收侧发送到发送侧在第一传输线上相邻的第一数据片段之间。

3. 发明授权

US08099537B2 Method, device, and system for transmitting data fragments over multiple transmission lines and techniques for stopping data transmission 有权
标题翻译：用于通过多条传输线传输数据片段的方法，设备和系统以及用于停止数据传输的技术
公开(公告)号：US08099537B2
公开(公告)日：2012-01-17
申请号：US12295407
申请日：2007-02-20
申请人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Noriaki Takeda , Takaharu Yoshida
发明人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Noriaki Takeda , Takaharu Yoshida
IPC分类号： G06F13/42 , G06F13/00 , G06F13/24 , G06F1/00 , G06F1/04 , G06F1/12 , G06F5/06
CPC分类号： H04L25/14
摘要： It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal. The invention provides a signal transmission method that is characterized in that a reception side and a transmission side partition data into a plurality of data fragments and send and receive the plurality of data fragments over at least two transmission lines, in that the transmission side transmits first data fragments of the plurality of data fragments over a first transmission line of the transmission lines, transmits data packets that include header information, a second data fragment that has the same bit length as the first data fragments, and footer information over a second transmission line other than the first transmission line, and transmits the first data fragments and the second data fragments in synchronization, and in that an interrupt signal for controlling the transmission side is transmitted from the reception side to the transmission side in a time slot that is an interval between first data fragments that are adjacent on the first transmission line.
摘要翻译：本发明的一个目的是抑制由于中断信号的传输引起的数据传输效率的下降。本发明提供了一种信号传输方法，其特征在于，接收侧和发送侧将数据划分成多个数据片段，并通过至少两条传输线发送和接收多个数据片段，其中发送侧首先发送在传输线的第一传输线上的多个数据片段的数据片段，通过第二传输线传输包括标题信息的数据包，具有与第一数据片段相同的位长的第二数据片段，以及页脚信息除了第一传输线之外，并且同步地发送第一数据片段和第二数据片段，并且用于控制发送侧的中断信号在作为间隔的时隙中的从接收侧发送到发送侧在第一传输线上相邻的第一数据片段之间。

4. 发明申请

US20090106460A1 REMOVABLE MEMORY DEVICE, PHASE SYNCHRONIZING METHOD, PHASE SYNCHRONIZING PROGRAM, MEDIUM RECORDING THE SAME, AND HOST TERMINAL 有权
标题翻译：可拆卸存储器件，相位同步方法，相位同步程序，记录其中的介质和终端
公开(公告)号：US20090106460A1
公开(公告)日：2009-04-23
申请号：US12295051
申请日：2007-02-20
申请人： Hiroshi Suenaga , Osamu Shibata , Noriaki Takeda , Toru Iwata , Takaharu Yoshida , Yoshiyuki Saito
发明人： Hiroshi Suenaga , Osamu Shibata , Noriaki Takeda , Toru Iwata , Takaharu Yoshida , Yoshiyuki Saito
IPC分类号： G06F3/00
CPC分类号： H04L7/10 , G06F1/12 , H04L7/0008 , H04L7/033 , H04L7/044 , H04L7/046
摘要： An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time. A removable memory device that transmits/receives data to and from a host terminal, which includes: a clock reception section 41 of receiving transmission/reception clock, which is used for transmitting/receiving data between the host terminal and the removable memory device, from the host terminal; a phase synchronization pattern generation section 45 of generating a phase synchronization pattern, which is for adjusting a phase of internal reception clock which the host terminal incorporates for receiving data from the removable memory device, based on the transmission/reception clock; and a transmission section of transmitting the generated phase synchronization pattern to the host terminal, and in which the phase synchronization pattern includes a first level signal which lasts for at least two cycles, and a second level signal which follows the first level signal and lasts for one cycle, is provided.
摘要翻译：本发明的目的是提供一种提高数据传输效率的技术，其允许同时正确地接收数据。一种向主机终端发送/接收数据的可移动存储装置，包括：用于在主机终端和可移动存储装置之间发送/接收数据的接收发送/接收时钟的时钟接收部分41，主机终端; 生成相位同步模式的相位同步模式生成部45，用于基于发送/接收时钟来调整主机终端结合的用于从可移动存储装置接收数据的内部接收时钟的相位; 以及发送部，其将生成的相位同步模式发送到主机终端，并且其中相位同步模式包括持续至少两个周期的第一电平信号，以及跟随第一电平信号并持续的第二电平信号提供一个循环。

5. 发明申请

US20050069032A1 Analog equalizer 审中-公开
标题翻译：模拟均衡器
公开(公告)号：US20050069032A1
公开(公告)日：2005-03-31
申请号：US10947382
申请日：2004-09-23
申请人： Takashi Hirata , Toru Iwata , Noriaki Takeda
发明人： Takashi Hirata , Toru Iwata , Noriaki Takeda
IPC分类号： H03K5/00 , H03K5/13 , H03K5/159 , H03L7/06 , H03L7/081 , H04B1/12 , H04B3/04 , H04B7/005 , H04L25/03
CPC分类号： H03L7/06 , H03K5/133 , H03K2005/00026 , H03L7/0805 , H03L7/0812 , H04L25/03885
摘要： An analog equalizer includes a mixer and an analog delay circuit. The mixer mixes an input signal and a delayed signal output from the analog delay circuit to output a mixed signal. The analog delay circuit delays the mixed signal output from the mixer to output a delayed signal.
摘要翻译：模拟均衡器包括混频器和模拟延迟电路。混合器混合输入信号和从模拟延迟电路输出的延迟信号以输出混合信号。模拟延迟电路延迟从混频器输出的混合信号以输出延迟信号。

6. 发明申请

US20080054957A1 Skew Correction Apparatus 审中-公开
标题翻译：倾斜校正装置
公开(公告)号：US20080054957A1
公开(公告)日：2008-03-06
申请号：US11587855
申请日：2004-12-08
申请人： Noriaki Takeda , Tohru Iwata
发明人： Noriaki Takeda , Tohru Iwata
IPC分类号： H03L7/06 , H03K3/037 , H03K5/00 , H03K5/13
CPC分类号： G06F1/10 , H03K5/133 , H03K5/135 , H03K5/15093 , H03K2005/00039 , H03K2005/00065 , H03L7/0812 , H03L7/0891 , H03L7/10 , H04L7/0008 , H04L7/0012 , H04L7/0037 , H04L7/033
摘要： A skew correction apparatus is composed of a variable delay line 200 for generating a delayed clock signal DCLK by delaying a clock signal CLK by a variable delay amount DT, a phase comparator 10 for comparing a phase of the delayed clock signal DCLK with transition of rising of a data signal DAT, a voltage holding means 6 for holding a voltage Vcntl for controlling the delay amount DT of the variable delay line 200, a charging/discharging means 30 for charging or discharging the voltage holding means 6, depending on a comparison result of the phase comparator 10, a charging means 40 for setting the voltage Vcntl of the voltage holding means 6 during initial setting, and a control circuit 500 for controlling the charging means 40.
摘要翻译：偏斜校正装置由用于通过将时钟信号CLK延迟可变延迟量DT来产生延迟时钟信号DCLK的可变延迟线200，用于将延迟时钟信号DCLK的相位与升序转换进行比较的相位比较器10 数据信号DAT的电压保持装置6，用于保持用于控制可变延迟线200的延迟量DT的电压Vcnt1的电压保持装置6，根据比较结果对电压保持装置6进行充电或放电的充电/放电装置30 相位比较器10的一个充电装置40，用于在初始设定期间设定电压保持装置6的电压Vcnt1的充电装置40和用于控制充电装置40的控制电路500。

7. 发明授权

US07046092B2 Amplifier circuit having signal detection function 失效
标题翻译：具有信号检测功能的放大器电路
公开(公告)号：US07046092B2
公开(公告)日：2006-05-16
申请号：US10861463
申请日：2004-06-07
申请人： Noriaki Takeda
发明人： Noriaki Takeda
IPC分类号： H03F3/08
CPC分类号： H03G3/3084
摘要： In an amplifier circuit, a main amplification section includes an amplifier for amplifying an input signal and a reference voltage generation circuit for generating a reference voltage from an output signal of the amplifier. Other main amplification sections each including the same internal structure are cascade-connected. A switch is provided for selecting any of amplifier outputs of these main amplification sections. A frequency component lower than that of an input signal to the amplifier circuit is removed by a filter circuit, and thereafter, the presence/absence of an input signal is detected by an amplitude detection circuit and a comparator. With such a structure, even if the input signal abruptly changes, e.g., immediately after the start of communication or immediately after the end of communication, an optical signal input is correctly detected and reproduced.
摘要翻译：在放大器电路中，主放大部分包括用于放大输入信号的放大器和用于从放大器的输出信号产生参考电压的参考电压产生电路。其他各个包括相同内部结构的主放大部分是级联的。提供用于选择这些主放大部分的放大器输出的开关。通过滤波电路除去低于放大电路的输入信号的频率成分，然后通过振幅检测电路和比较器检测输入信号的有无。利用这种结构，即使输入信号突然变化，例如在通信开始之后或紧接在通信结束之后，光信号输入被正确检测和再现。

8. 发明申请

US20100271142A1 COUPLED RING OSCILLATOR AND METHOD FOR LAYING OUT THE SAME 有权
标题翻译：耦合振荡器及其相结合的方法
公开(公告)号：US20100271142A1
公开(公告)日：2010-10-28
申请号：US12831715
申请日：2010-07-07
申请人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
发明人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.
摘要翻译：耦合环形振荡器包括n个环形振荡器（20），每个环形振荡器（20）包括m个逆变器电路（10）和相位耦合回路（40），其中m×n个相位耦合电路（30）点在某一相位模式下，相互连接形成一个回路。逆变器电路（10）彼此连接的连接点和相位耦合电路（30）彼此连接的连接点彼此连接; 并且每个逆变器电路（10）连接在将相耦合电路（30）以一定比例分成两部分的两个点之间。

9. 发明授权

US07777580B2 Coupled ring oscillator and method for laying out the same 有权
标题翻译：耦合环形振荡器及其布置方法
公开(公告)号：US07777580B2
公开(公告)日：2010-08-17
申请号：US11884270
申请日：2006-05-25
申请人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
发明人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.
摘要翻译：耦合环形振荡器包括n个环形振荡器（20），每个环形振荡器（20）包括m个逆变器电路（10）和相位耦合回路（40），其中m×n个相位耦合电路（30）点在某一相位模式下，相互连接形成一个回路。逆变器电路（10）彼此连接的连接点和相位耦合电路（30）彼此连接的连接点彼此连接; 并且每个逆变器电路（10）连接在将相耦合电路（30）以一定比例分成两部分的两个点之间。

10. 发明申请

US20050012549A1 Amplifier circuit having signal detection function 失效
标题翻译：具有信号检测功能的放大器电路
公开(公告)号：US20050012549A1
公开(公告)日：2005-01-20
申请号：US10861463
申请日：2004-06-07
申请人： Noriaki Takeda
发明人： Noriaki Takeda
IPC分类号： H03F3/45 , H03F3/08 , H03G3/30 , H04B10/2507 , H04B10/40 , H04B10/50 , H04B10/524 , H04B10/60 , H04B10/69 , H03G3/20
CPC分类号： H03G3/3084
摘要： In an amplifier circuit, a main amplification section includes an amplifier for amplifying an input signal and a reference voltage generation circuit for generating a reference voltage from an output signal of the amplifier. Other main amplification sections each including the same internal structure are cascade-connected. A switch is provided for selecting any of amplifier outputs of these main amplification sections. A frequency component lower than that of an input signal to the amplifier circuit is removed by a filter circuit, and thereafter, the presence/absence of an input signal is detected by an amplitude detection circuit and a comparator. With such a structure, even if the input signal abruptly changes, e.g., immediately after the start of communication or immediately after the end of communication, an optical signal input is correctly detected and reproduced.
摘要翻译：在放大器电路中，主放大部分包括用于放大输入信号的放大器和用于从放大器的输出信号产生参考电压的参考电压产生电路。其他各个包括相同内部结构的主放大部分是级联的。提供用于选择这些主放大部分的放大器输出的开关。通过滤波电路除去低于放大电路的输入信号的频率成分，然后通过振幅检测电路和比较器检测输入信号的有无。利用这种结构，即使输入信号突然变化，例如在通信开始之后或紧接在通信结束之后，光信号输入被正确检测和再现。

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