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1. 发明授权

US08487374B2 Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US08487374B2
公开(公告)日：2013-07-16
申请号：US13234802
申请日：2011-09-16
申请人： Hiroshi Ohta , Yasuto Sumi , Kiyoshi Kimura , Junji Suzuki , Hiroyuki Irifune , Wataru Saito , Syotaro Ono
发明人： Hiroshi Ohta , Yasuto Sumi , Kiyoshi Kimura , Junji Suzuki , Hiroyuki Irifune , Wataru Saito , Syotaro Ono
IPC分类号： H01L29/66
CPC分类号： H01L29/78 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/42356 , H01L29/42372 , H01L29/7811 , H01L29/7813
摘要： In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other.
摘要翻译：通常，根据一个实施例，功率半导体器件包括在第一半导体层上的第一导电类型的第一柱状区域，第二柱状区域和外延层。第一支柱区域由第一导电类型的多个第一支柱层和沿第一方向交替布置的第一导电类型的多个第二支柱层组成。第二柱状区域沿着第一方向与第一柱状区域相邻，并且具有第二导电型的第三柱状层，第一导电型的第四柱状层和第二导电型的第五柱状层沿着第一个方向。多个第二导电类型的第二基极层分别电连接到第三柱层和第五柱层上并彼此间隔开。

2. 发明授权

US08872261B2 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US08872261B2
公开(公告)日：2014-10-28
申请号：US13607255
申请日：2012-09-07
申请人： Hiroyuki Irifune , Wataru Saito , Yasuto Sumi , Kiyoshi Kimura , Hiroshi Ohta , Junji Suzuki
发明人： Hiroyuki Irifune , Wataru Saito , Yasuto Sumi , Kiyoshi Kimura , Hiroshi Ohta , Junji Suzuki
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/404 , H01L29/7811
摘要： A semiconductor device includes first, second, and third semiconductor layers each having multiple diffusion layers. The first direction widths of the first diffusion layers are the same. The amount of impurity within the first diffusion layers gradually increases from the bottom end towards the top end of the first semiconductor layer. The first direction widths of the second diffusion layers are the same. The amounts of impurity within the second diffusion layers are the same. The first direction widths of the third diffusion layers are narrower than the first direction widths of the first diffusion layers and the first direction widths of the second diffusion layers at the same level, and gradually become narrower from the bottom end towards the top end of the third semiconductor layer. The amount of impurity within the third diffusion layers are the same.
摘要翻译：半导体器件包括各自具有多个扩散层的第一，第二和第三半导体层。第一扩散层的第一方向宽度是相同的。第一扩散层内的杂质量从第一半导体层的底端向顶端逐渐增加。第二扩散层的第一方向宽度相同。第二扩散层内的杂质量相同。第三扩散层的第一方向宽度比第一扩散层的第一方向宽度和第二扩散层的第一方向宽度在相同水平处窄，并且从第一扩散层的第一方向宽度逐渐变窄到第三半导体层。第三扩散层内的杂质量相同。

3. 发明授权

US08680606B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08680606B2
公开(公告)日：2014-03-25
申请号：US13424344
申请日：2012-03-19
申请人： Hiroshi Ohta , Yasuto Sumi , Kiyoshi Kimura , Junji Suzuki , Hiroyuki Irifune
发明人： Hiroshi Ohta , Yasuto Sumi , Kiyoshi Kimura , Junji Suzuki , Hiroyuki Irifune
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/4238 , H01L29/66712
摘要： A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer provided thereon, mutually separated columnar third semiconductor layers of a second conductivity type extending within the second semiconductor layer, island-like fourth semiconductor layers of the second conductivity type provided on the third semiconductor layers, fifth semiconductor layers of the first conductivity type, sixth semiconductor layers of the second conductivity type, a gate electrode, a first electrode, and a second electrode. The fifth semiconductor layers are selectively provided on the fourth semiconductor layers. The sixth semiconductor layer electrically connects two adjacent fourth semiconductor layers. The first electrode is in electrical connection with the first semiconductor. The second electrode is in electrical connection with the fourth semiconductor layers and the fifth semiconductor layers via the openings in the gate electrode.
摘要翻译：功率半导体器件包括第一导电类型的第一半导体层，设置在其上的第二半导体层，在第二半导体层内延伸的第二导电类型的相互分离的柱状第三半导体层，第二导电类型的岛状第四半导体层提供在第三半导体层上的第一半导体层，第一导电类型的第五半导体层，第二导电类型的第六半导体层，栅电极，第一电极和第二电极。第五半导体层选择性地设置在第四半导体层上。第六半导体层电连接两个相邻的第四半导体层。第一电极与第一半导体电连接。第二电极经由栅电极中的开口与第四半导体层和第五半导体层电连接。

4. 发明申请

US20110291181A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110291181A1
公开(公告)日：2011-12-01
申请号：US13149345
申请日：2011-05-31
申请人： Hiroyuki IRIFUNE , Yasuto Sumi , Kiyoshi Kimura , Hiroshi Ohta
发明人： Hiroyuki IRIFUNE , Yasuto Sumi , Kiyoshi Kimura , Hiroshi Ohta
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66712 , H01L29/0626 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/404 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： According to one embodiment, a semiconductor device including a cell region and a terminal region includes a first semiconductor region of a first conductivity type, semiconductor pillars of the first and a second conductivity type, a second semiconductor region of the second conductivity type, and a third semiconductor region of the first conductivity type. The semiconductor pillars of the first and second conductivity type are and arranged alternately on the first semiconductor region. The second semiconductor region is provided on the semiconductor pillar of the second conductivity type. The third semiconductor region is provided on the second semiconductor region. A semiconductor pillar other than a semiconductor pillar most proximal to the terminal region is provided in a stripe configuration. The semiconductor pillar most proximal to the terminal region includes regions having a high and a low impurity concentration. The regions are provided alternately.
摘要翻译：根据一个实施例，包括单元区域和端子区域的半导体器件包括第一导电类型的第一半导体区域，第一和第二导电类型的半导体柱，第二导电类型的第二半导体区域和第一导电类型的第三半导体区域。第一和第二导电类型的半导体柱交替地布置在第一半导体区域上。第二半导体区域设置在第二导电类型的半导体柱上。第三半导体区域设置在第二半导体区域上。最靠近端子区域的半导体柱以外的半导体柱设置成条状。最靠近末端区域的半导体柱包括具有高和低杂质浓度的区域。这些区域交替地设置。

5. 发明授权

US08643056B2 Power semiconductor device and method of manufacturing the same 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US08643056B2
公开(公告)日：2014-02-04
申请号：US13229203
申请日：2011-09-09
申请人： Kiyoshi Kimura , Yasuto Sumi , Hiroshi Ohta , Hiroyuki Irifune
发明人： Kiyoshi Kimura , Yasuto Sumi , Hiroshi Ohta , Hiroyuki Irifune
IPC分类号： H01L29/66
CPC分类号： H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/7811 , H01L29/872
摘要： A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers. The plurality of third second-conductivity-type pillar layers are arranged on the first epitaxial layer.
摘要翻译：功率半导体器件包括第一导电类型的第一半导体层，第一漂移层和第二漂移层。第一漂移层包括第一导电类型的第一外延层，多个第一第一导电型柱层和多个第一第二导电型柱层。第二漂移层形成在第一漂移层上，并且包括第一导电类型的第二外延层，多个第二第二导电型柱层，多个第二第一导电型柱层，多个第二导电型柱层第三第二导电型柱层和多个第三第一导电型柱层。多个第二第二导电型柱层与第一第二导电型柱层连接。多个第二第一导电型柱层与第一第一导电型柱层连接。多个第三第二导电型柱层布置在第一外延层上。

6. 发明授权

US08610210B2 Power semiconductor device and method for manufacturing same 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US08610210B2
公开(公告)日：2013-12-17
申请号：US12840201
申请日：2010-07-20
申请人： Hiroshi Ohta , Yasuto Sumi , Kiyoshi Kimura , Wataru Sekine , Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
发明人： Hiroshi Ohta , Yasuto Sumi , Kiyoshi Kimura , Wataru Sekine , Wataru Saito , Syotaro Ono , Munehisa Yabuzaki , Nana Hatano , Miho Watanabe
IPC分类号： H01L29/66
CPC分类号： H01L29/66712 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/7811
摘要： According to one embodiment, a power semiconductor device includes a first semiconductor layer, and first, second and third semiconductor regions. The first semiconductor layer has a first conductivity type. The first semiconductor regions have a second conductivity type, and are formed with periodicity in a lateral direction in a second semiconductor layer of the first conductivity type. The second semiconductor layer is provided on a major surface of the first semiconductor layer in a device portion with a main current path formed in a vertical direction generally perpendicular to the major surface and in a terminal portion provided around the device portion. The second semiconductor region has the first conductivity type and is a portion of the second semiconductor layer sandwiched between adjacent ones of the first semiconductor regions. The third semiconductor regions have the second conductivity type and are provided below the first semiconductor regions in the terminal portion.
摘要翻译：根据一个实施例，功率半导体器件包括第一半导体层以及第一，第二和第三半导体区域。第一半导体层具有第一导电类型。第一半导体区域具有第二导电类型，并且在第一导电类型的第二半导体层中在横向方向上形成周期性。第二半导体层设置在器件部分的第一半导体层的主表面上，其主电流通道形成在大体上垂直于主表面的垂直方向上，以及设置在器件部分周围的端子部分中。第二半导体区域具有第一导电类型，并且是夹在相邻的第一半导体区域中的第二半导体层的一部分。第三半导体区域具有第二导电类型并且设置在端子部分中的第一半导体区域的下方。

7. 发明授权

US07989910B2 Semiconductor device including a resurf region with forward tapered teeth 有权
标题翻译：半导体装置包括具有前锥形齿的复原区域
公开(公告)号：US07989910B2
公开(公告)日：2011-08-02
申请号：US12252872
申请日：2008-10-16
申请人： Wataru Saito , Syotaro Ono , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Nana Hatano
发明人： Wataru Saito , Syotaro Ono , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Nana Hatano
IPC分类号： H01L29/66
CPC分类号： H01L29/0634 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/7811
摘要： A semiconductor device includes an n+ type semiconductor substrate 1 and a super junction region that has, on the top of the substrate 1, an n and p type pillar regions 2 and 3 provided alternately. The device also includes, in the top surface of the super junction region, a p type base region 4 and an n type source layer 5. The device also includes a gate electrode 7 on the region 4 and layer 5 via a gate-insulating film 6, a drain electrode 9 on the bottom of the substrate 1, and a source electrode 8 on the top of the substrate 1. In the top surface of the super junction region in the terminal region, a RESURF region 10 is formed. The RESURF region has a comb-like planar shape with repeatedly-formed teeth having tips facing the end portion of the terminal region.
摘要翻译：半导体器件包括n +型半导体衬底1和超结区，其在衬底1的顶部上交替设置n和p型柱状区域2,3。该器件还在超结区域的顶表面中包括ap型基极区域4和n型源极层5.该器件还包括位于区域4上的栅电极7和通过栅极绝缘膜6的层5 ，基板1底部的漏电极9以及基板1顶部的源极8.在端子区域的超结区域的上表面形成有RESURF区域10。 RESURF区域具有梳状平面形状，具有重复形成的齿，其尖端面向终端区域的端部。

8. 发明授权

US07919824B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07919824B2
公开(公告)日：2011-04-05
申请号：US12403881
申请日：2009-03-13
申请人： Syotaro Ono , Wataru Saito , Nana Hatano , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Miho Watanabe
发明人： Syotaro Ono , Wataru Saito , Nana Hatano , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Miho Watanabe
IPC分类号： H01L27/088
CPC分类号： H01L29/66712 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/7395 , H01L29/7811
摘要： A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region have an impurity amount such that it becomes smaller as being closer to the circumference of the corner part.
摘要翻译：半导体器件包括具有交替设置在半导体衬底上的第一导电型第一半导体柱区域和第二导电型第二半导体柱区域的超结区域。终端区域中的第一半导体柱区域和第二半导体柱区域具有由半导体衬底的顶表面上的第一半导体柱区域和第二半导体柱区域的交替层叠形成的叠层形式。终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域显示杂质浓度分布，使得多个杂质浓度峰值周期性出现。终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域具有使得随着角部更靠近圆周而变小的杂质量。

9. 发明授权

US07737469B2 Semiconductor device having superjunction structure formed of p-type and n-type pillar regions 失效
标题翻译：具有由p型和n型柱状区域形成的超结构结构的半导体装置
公开(公告)号：US07737469B2
公开(公告)日：2010-06-15
申请号：US11748869
申请日：2007-05-15
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/74
CPC分类号： H01L29/872 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/402 , H01L29/404 , H01L29/41741 , H01L29/7395 , H01L29/7397 , H01L29/7722 , H01L29/7806 , H01L29/7811 , H01L29/8611
摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.
摘要翻译：半导体器件包括：第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域，与半导体层的主表面上的第一半导体柱区域相邻设置，第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。高电阻半导体层的掺杂浓度低于第一半导体柱区域。边界区域设置在设备中心区域和边缘终端部分之间。边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。

10. 发明申请

US20080290403A1 SEMICONDUCTOR APPARATUS 失效
公开(公告)号：US20080290403A1
公开(公告)日：2008-11-27
申请号：US12123072
申请日：2008-05-19
申请人： Syotaro ONO , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Syotaro ONO , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/7395 , H01L29/861 , H01L29/868 , H01L29/872
摘要： A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer.
摘要翻译：半导体装置包括第一半导体层，设置在第一半导体层的主表面上的第二半导体层，设置在主表面上并与第二半导体层相邻的第三半导体层，设置在主体上的端接半导体层在器件区域外的终端区域中的第一半导体层的表面，沟道阻挡层和沟道停止电极。沟道阻挡层设置成与终端半导体层外部的最外周部分中的第一半导体层的主表面上的端接半导体层接触，并且具有比端接半导体层更高的杂质浓度。通道阻挡电极设置在通道阻挡层的表面的至少一部分上，并且朝向端子半导体层突出超过通道阻挡层的至少表面部分。

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