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1. 发明授权

US08717137B2 On-chip inductor using redistribution layer and dual-layer passivation 有权
标题翻译：片上电感使用再分配层和双层钝化
公开(公告)号：US08717137B2
公开(公告)日：2014-05-06
申请号：US11443171
申请日：2006-05-31
申请人： Henry Kuo-Shun Chen , Guang-Jye Shiau , Akira Ito
发明人： Henry Kuo-Shun Chen , Guang-Jye Shiau , Akira Ito
IPC分类号： H01F5/00
CPC分类号： H01L28/10 , H01F5/00 , H01F17/0013 , H01F41/041 , H01L23/5227 , H01L23/525 , H01L24/10 , H01L24/13 , H01L27/08 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19042 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00014
摘要： A system and method utilize a redistribution layer in a flip-chip or wirebond package, which is also used to route signals to bumps, as a layer for the construction of an on-chip inductor or a layer of a multiple-layer on-chip inductor. In one example, the redistribution layer is surrounded by dual-layer passivation to protect it, and the inductor formed thereby, from the environment and isolate it, and the inductor formed thereby, from the metal layer beneath it.
摘要翻译：一种系统和方法利用倒装芯片或引线键合封装中的再分布层，其也用于将信号路由到凸点，作为用于构建片上电感器的层或多层片上层电感。在一个示例中，再分布层被双层钝化包围，以保护它，并且从环境形成的电感器从其环境中分离出来并将其与其形成的电感器从其下方的金属层隔离开来。

2. 发明申请

US20070279176A1 On-chip inductor using redistribution layer and dual-layer passivation 有权
标题翻译：片上电感使用再分配层和双层钝化
公开(公告)号：US20070279176A1
公开(公告)日：2007-12-06
申请号：US11443171
申请日：2006-05-31
申请人： Henry Kuo-Shun Chen , Guang-Jye Shiau , Akira Ito
发明人： Henry Kuo-Shun Chen , Guang-Jye Shiau , Akira Ito
IPC分类号： H01F5/00
CPC分类号： H01L28/10 , H01F5/00 , H01F17/0013 , H01F41/041 , H01L23/5227 , H01L23/525 , H01L24/10 , H01L24/13 , H01L27/08 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/056 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19042 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00014
摘要： A system and method utilize a redistribution layer in a flip-chip or wirebond package, which is also used to route signals to bumps, as a layer for the construction of an on-chip inductor or a layer of a multiple-layer on-chip inductor. In one example, the redistribution layer is surrounded by dual-layer passivation to protect it, and the inductor formed thereby, from the environment and isolate it, and the inductor formed thereby, from the metal layer beneath it.
摘要翻译：一种系统和方法利用倒装芯片或引线键合封装中的再分布层，其也用于将信号路由到凸点，作为用于构建片上电感器的层或多层片上层电感。在一个示例中，再分布层被双层钝化包围，以保护它，并且从环境形成的电感器从其环境中分离出来并将其与其形成的电感器从其下方的金属层隔离开来。

3. 发明授权

US07855414B2 Semiconductor device with increased breakdown voltage 有权
标题翻译：具有提高击穿电压的半导体器件
公开(公告)号：US07855414B2
公开(公告)日：2010-12-21
申请号：US11580961
申请日：2006-10-16
申请人： Akira Ito , Henry Kuo-Shun Chen
发明人： Akira Ito , Henry Kuo-Shun Chen
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/086 , H01L29/0865 , H01L29/1045 , H01L29/1083 , H01L29/456 , H01L29/66659 , H01L29/7835
摘要： Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.
摘要翻译：优化使用常规互补金属氧化物硅（CMOS）逻辑铸造技术制造的金属氧化物硅场效应晶体管（MOSFET）器件的注入结构，以增加击穿电压。用于优化注入结构的技术包括轻微地注入栅极区域，使漏极区域从栅极区域移位，以及将P阱和N阱区域彼此相邻地注入，而不会在其间形成隔离区域。

4. 发明申请

US20080023760A1 Semiconductor device with increased breakdown voltage 有权
标题翻译：半导体器件具有增加的击穿电压
公开(公告)号：US20080023760A1
公开(公告)日：2008-01-31
申请号：US11580961
申请日：2006-10-16
申请人： Akira Ito , Henry Kuo-Shun Chen
发明人： Akira Ito , Henry Kuo-Shun Chen
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/086 , H01L29/0865 , H01L29/1045 , H01L29/1083 , H01L29/456 , H01L29/66659 , H01L29/7835
摘要： Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-Well regions adjacent to one another without an isolation region in between.
摘要翻译：优化使用常规互补金属氧化物硅（CMOS）逻辑铸造技术制造的金属氧化物硅场效应晶体管（MOSFET）器件的注入结构，以增加击穿电压。用于优化注入结构的技术包括轻微注入栅极区域，使漏极区域从栅极区域移位，以及将P阱和N阱区域彼此相邻地注入，而不会在其间形成隔离区域。

5. 发明申请

US20080246080A1 Shallow trench isolation (STI) based laterally diffused metal oxide semiconductor (LDMOS) 审中-公开
标题翻译：基于横沟扩散金属氧化物半导体（LDMOS）的浅沟槽隔离（STI）
公开(公告)号：US20080246080A1
公开(公告)日：2008-10-09
申请号：US12155628
申请日：2008-06-06
申请人： Akira Ito , Henry Kuo-Shun Chen
发明人： Akira Ito , Henry Kuo-Shun Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/086 , H01L29/0865 , H01L29/1083 , H01L29/456 , H01L29/66659
摘要： An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A third heavily doped region represents a gate region of the semiconductor device. The semiconductor device further includes a shallow trench isolation (STI) region to increase the resistance from the drain region to the source region. The STI region includes a first side vertically aligned with a second side of the gate region. The STI region extends from the first side to a second side in contact with a second side of the drain region. The breakdown voltage of the n-type semiconductor device is directly proportional to a vertical length, or a depth, of the first side and/or the second side of the STI region. The horizontal length, or distance from the first side to the second side, of the STI region does not substantially contribute to the breakdown voltage of the semiconductor device. As a result, a conventional CMOS logic foundry technology may fabricate the STI region of the semiconductor device using a low operating voltage process minimum design rule.
摘要翻译：公开了一种用于增加半导体器件的击穿电压的装置。半导体器件包括表示源极区的第一重掺杂区域。第二重掺杂区域表示半导体器件的漏极区域。第三重掺杂区域表示半导体器件的栅极区域。半导体器件还包括浅沟槽隔离（STI）区域，以增加从漏区到源极区的电阻。 STI区域包括与栅极区域的第二侧垂直对准的第一侧面。 STI区从第一侧延伸到与漏区的第二侧接触的第二侧。 n型半导体器件的击穿电压与STI区域的第一侧和/或第二面的垂直长度或深度成正比。 STI区域的水平长度或从第一侧到第二侧的距离基本上不会有助于半导体器件的击穿电压。结果，传统的CMOS逻辑铸造技术可以使用低工作电压工艺最小设计规则来制造半导体器件的STI区域。

6. 发明授权

US08598670B2 Semiconductor device with increased breakdown voltage 有权
标题翻译：半导体器件具有增加的击穿电压
公开(公告)号：US08598670B2
公开(公告)日：2013-12-03
申请号：US12943330
申请日：2010-11-10
申请人： Akira Ito , Henry Kuo-Shun Chen
发明人： Akira Ito , Henry Kuo-Shun Chen
IPC分类号： H01L21/02
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/086 , H01L29/0865 , H01L29/1045 , H01L29/1083 , H01L29/456 , H01L29/66659 , H01L29/7835
摘要： Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between.
摘要翻译：优化使用常规互补金属氧化物硅（CMOS）逻辑铸造技术制造的金属氧化物硅场效应晶体管（MOSFET）器件的注入结构，以增加击穿电压。用于优化注入结构的技术包括轻微地注入栅极区域，使漏极区域从栅极区域移位，以及将P阱和N阱区域彼此相邻地注入，而不会在其间形成隔离区域。

7. 发明申请

US20110169079A1 Semiconductor device having an overlapping multi-well implant and method for fabricating same 审中-公开
标题翻译：具有重叠多孔注入的半导体器件及其制造方法
公开(公告)号：US20110169079A1
公开(公告)日：2011-07-14
申请号：US12657162
申请日：2010-01-14
申请人： Akira Ito , Henry Kuo-Shun Chen , Bruce Chih-Chieh Shen
发明人： Akira Ito , Henry Kuo-Shun Chen , Bruce Chih-Chieh Shen
IPC分类号： H01L29/78 , H01L21/30
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/66659 , H01L29/7835
摘要： According to one embodiment, a semiconductor device having an overlapping multi-well implant comprises an isolation structure formed in a semiconductor body, a first well implant formed in the semiconductor body surrounding the isolation structure, and a second well implant overlapping at least a portion of the first well implant. The disclosed semiconductor device, which may be an NMOS or PMOS device, can further comprise a gate formed over the semiconductor body adjacent to the isolation structure, wherein the first well implant extends a first lateral distance under the gate and the second well implant extends a second lateral distance under the gate, and wherein the first and second lateral distances may be different. In one embodiment, the disclosed semiconductor device is fabricated as part of an integrated circuit including a power management circuit or a power amplifier.
摘要翻译：根据一个实施例，具有重叠多阱注入的半导体器件包括形成在半导体本体中的隔离结构，形成在半导体主体中的围绕隔离结构的第一阱注入，以及重叠至少部分第一口植入物。所公开的可以是NMOS或PMOS器件的半导体器件还可以包括形成在半导体主体上方的与隔离结构相邻的栅极，其中第一阱注入在栅极下延伸第一横向距离，第二阱注入延伸一个栅极下方的第二横向距离，并且其中第一和第二横向距离可以不同。在一个实施例中，所公开的半导体器件被制造为包括功率管理电路或功率放大器的集成电路的一部分。

8. 发明申请

US20130082351A1 Method for Fabricating a MIM Capacitor Having a Local Interconnect Metal Electrode and Related Structure 有权
标题翻译：具有局部互连金属电极和相关结构的MIM电容器的制造方法
公开(公告)号：US20130082351A1
公开(公告)日：2013-04-04
申请号：US13248823
申请日：2011-09-29
申请人： Xiangdong Chen , Henry Kuo-Shun Chen , Wei Xia , Bruce Chih-Chieh Shen
发明人： Xiangdong Chen , Henry Kuo-Shun Chen , Wei Xia , Bruce Chih-Chieh Shen
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.
摘要翻译：根据一个示例性实施例，在半导体管芯中制造金属 - 绝缘体 - 金属（MIM）电容器的方法包括在位于半导体管芯的第一金属化层下方的器件层上形成底部电容器电极，并形成顶部电容器形成在底部电容器电极上的层间势垒电介质上的电极。顶部电容器电极由局部互连金属形成，用于连接器件层中形成的器件。在一个实施例中，底部电容器电极由栅极金属形成。该方法还可以包括在第一金属化层中和顶部电容器电极上形成金属板，并将金属板连接到底部电容器电极以提供增加的电容密度。

9. 发明申请

US20100314691A1 Method for selective gate halo implantation in a semiconductor die and related structure 有权
标题翻译：半导体晶片中选择性栅晕注入的方法及相关结构
公开(公告)号：US20100314691A1
公开(公告)日：2010-12-16
申请号：US12456065
申请日：2009-06-10
申请人： Xiangdong Chen , Henry Kuo-Shun Chen , Kent Charles Oertle , Jennifer Chiao
发明人： Xiangdong Chen , Henry Kuo-Shun Chen , Kent Charles Oertle , Jennifer Chiao
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66575 , H01L21/26586 , H01L29/1045 , H01L29/66537 , H01L29/78
摘要： According to one embodiment, a method for selective gate halo implantation includes forming at least one gate having a first orientation and at least one gate having a second orientation over a substrate. The method further includes performing a halo implant over the substrate. The first orientation allows a halo implanted area to be formed under the at least one gate having the first orientation and the second orientation prevents a halo implanted area from forming under the at least one gate having the second orientation. The halo implant is performed without forming a mask over the at least one gate having the first orientation or the at least one gate having the second orientation. The at least one gate having the first orientation can be used in a low voltage region of a substrate, while the at least one gate having the second orientation can be used in a high voltage region.
摘要翻译：根据一个实施例，用于选择性栅极晕晕注入的方法包括在衬底上形成具有第一取向的至少一个栅极和具有第二取向的至少一个栅极。该方法还包括在衬底上执行晕轮植入。第一取向允许在具有第一取向的至少一个栅极下方形成光晕注入区域，并且第二取向防止在具有第二取向的至少一个栅极下形成光晕注入区域。在没有在具有第一取向的至少一个栅极或具有第二取向的至少一个栅极上形成掩模的情况下执行光晕注入。具有第一取向的至少一个栅极可用于衬底的低电压区域，而具有第二取向的至少一个栅极可用于高电压区域。

10. 发明授权

US09041153B2 MIM capacitor having a local interconnect metal electrode and related structure 有权
标题翻译：具有局部互连金属电极和相关结构的MIM电容器
公开(公告)号：US09041153B2
公开(公告)日：2015-05-26
申请号：US13248823
申请日：2011-09-29
申请人： Xiangdong Chen , Henry Kuo-Shun Chen , Wei Xia , Bruce Chih-Chieh Shen
发明人： Xiangdong Chen , Henry Kuo-Shun Chen , Wei Xia , Bruce Chih-Chieh Shen
IPC分类号： H01L29/92 , H01L23/522 , H01L49/02
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.
摘要翻译：根据一个示例性实施例，在半导体管芯中制造金属 - 绝缘体 - 金属（MIM）电容器的方法包括在位于半导体管芯的第一金属化层下方的器件层上形成底部电容器电极，并形成顶部电容器形成在底部电容器电极上的层间势垒电介质上的电极。顶部电容器电极由局部互连金属形成，用于连接器件层中形成的器件。在一个实施例中，底部电容器电极由栅极金属形成。该方法还可以包括在第一金属化层中和顶部电容器电极上形成金属板，并将金属板连接到底部电容器电极以提供增加的电容密度。

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