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1. 发明申请

US20080054477A1 Processing with Reduced Line End Shortening Ratio 有权
标题翻译：减少线端缩短比例的处理
公开(公告)号：US20080054477A1
公开(公告)日：2008-03-06
申请号：US11843629
申请日：2007-08-22
申请人： Hai CONG , Wei Loong LOH , Krishan GOPAL , Xin ZHANG , Mei Sheng ZHOU , Pradeep Ramachandramurthy YELEHANKA
发明人： Hai CONG , Wei Loong LOH , Krishan GOPAL , Xin ZHANG , Mei Sheng ZHOU , Pradeep Ramachandramurthy YELEHANKA
IPC分类号： H01L23/48 , H01L21/311
CPC分类号： H01L21/32137 , H01L21/32139
摘要： A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.
摘要翻译：用于形成具有减少的线端缩短（LES）的器件特征的方法包括修整器件特征以在蚀刻期间实现期望的子接地规则临界尺寸以形成器件特征。

2. 发明申请

US20120012940A1 INTEGRATED CIRCUIT AND METHOD OF FABRICATION THEREOF 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US20120012940A1
公开(公告)日：2012-01-19
申请号：US13241215
申请日：2011-09-23
申请人： Jinping LIU , Hai CONG , Binbin ZHOU , Alex KH SEE , Mei Sheng ZHOU , Liang Choo HSIA
发明人： Jinping LIU , Hai CONG , Binbin ZHOU , Alex KH SEE , Mei Sheng ZHOU , Liang Choo HSIA
IPC分类号： H01L27/092
CPC分类号： H01L21/823468 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.
摘要翻译：一种形成集成电路结构的方法，包括以下步骤：在晶片的表面上形成第一和第二器件区域，在第一器件区域中的第一栅极堆叠的侧壁上形成第一宽度的间隔物，形成间隔物在第二装置区域中的第二栅极堆叠的侧壁上具有第二宽度，第一宽度不同于第二宽度。

3. 发明申请

US20090289309A1 METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS 有权
标题翻译：降低集成电路中硅氧化物缺陷的方法
公开(公告)号：US20090289309A1
公开(公告)日：2009-11-26
申请号：US12124177
申请日：2008-05-21
申请人： Jianhui YE , Huang LIU , Alex KH SEE , Wei LU , Hai CONG , Hui Peng KOH , Mei Sheng ZHOU , Liang Choo HSIA
发明人： Jianhui YE , Huang LIU , Alex KH SEE , Wei LU , Hai CONG , Hui Peng KOH , Mei Sheng ZHOU , Liang Choo HSIA
IPC分类号： H01L29/00 , H01L21/311
CPC分类号： H01L29/665 , H01L21/31116 , H01L29/6653 , H01L29/78
摘要： A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
摘要翻译：描述了在集成电路（IC）中形成硅化物触点的方法。在水解过程期间进行间隔物拉回蚀刻以减少间隔物与间隔物底切下的源/漏硅化物接触之间的应力。这样可以防止表面缺陷进入衬底，从而使硅化物管缺陷的发生最小化。间隔物拉回蚀刻可以在第一退火步骤之后进行以形成硅化物接触。

4. 发明申请

US20100267236A1 METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS 有权
标题翻译：降低集成电路中硅氧化物缺陷的方法
公开(公告)号：US20100267236A1
公开(公告)日：2010-10-21
申请号：US12825325
申请日：2010-06-28
申请人： Jianhui YE , Huang LIU , Alex KH SEE , Wei LU , Hai CONG , Hui Peng KOH , Mei Sheng ZHOU , Liang Choo HSIA
发明人： Jianhui YE , Huang LIU , Alex KH SEE , Wei LU , Hai CONG , Hui Peng KOH , Mei Sheng ZHOU , Liang Choo HSIA
IPC分类号： H01L21/28
CPC分类号： H01L29/665 , H01L21/31116 , H01L29/6653 , H01L29/78
摘要： A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
摘要翻译：描述了在集成电路（IC）中形成硅化物触点的方法。在水解过程期间进行间隔物拉回蚀刻以减少间隔物与间隔物底切下的源/漏硅化物接触之间的应力。这样可以防止表面缺陷进入衬底，从而使硅化物管缺陷的发生最小化。间隔物拉回蚀刻可以在第一退火步骤之后进行以形成硅化物接触。

5. 发明申请

US20090140292A1 INTEGRATED CIRCUIT AND METHOD OF FABRICATION THEREOF 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US20090140292A1
公开(公告)日：2009-06-04
申请号：US11946843
申请日：2007-11-29
申请人： Jinping LIU , Hai CONG , Binbin ZHOU , Alex KH SEE , Mei Sheng ZHOU , Liang Choo HSIA
发明人： Jinping LIU , Hai CONG , Binbin ZHOU , Alex KH SEE , Mei Sheng ZHOU , Liang Choo HSIA
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823468 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.
摘要翻译：一种形成集成电路结构的方法，包括以下步骤：在晶片的表面上形成第一和第二器件区域，在第一器件区域中的第一栅极堆叠的侧壁上形成第一宽度的间隔物，形成间隔物在第二装置区域中的第二栅极堆叠的侧壁上具有第二宽度，第一宽度不同于第二宽度。

6. 发明申请

US20080076244A1 Damascene Contact Structure for Integrated Circuits 有权
标题翻译：集成电路的大马士革接触结构
公开(公告)号：US20080076244A1
公开(公告)日：2008-03-27
申请号：US11535069
申请日：2006-09-26
申请人： Jian Hui YE , Mei Sheng ZHOU
发明人： Jian Hui YE , Mei Sheng ZHOU
IPC分类号： H01L21/44
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/76846 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L23/53238
摘要： Interconnects for integrated circuits, such as damascene structures are formed using a hard mask. The hard mask is formed from, for example, high-k dielectric material such as hafnium oxide or other materials having high etch selectivity to the interconnect dielectric material. This enables a thin mask to etch vias and trenches in the interconnect dielectric layer, avoiding the problems associated with the use of thick mask layers, such as contact hole striations and small depth of focus, which can result in shorts or opens.
摘要翻译：集成电路的互连（如镶嵌结构）使用硬掩模形成。硬掩模由例如高k电介质材料形成，例如氧化铪或对互连电介质材料具有高蚀刻选择性的其它材料。这使得薄掩模能够蚀刻互连电介质层中的通孔和沟槽，从而避免与使用厚掩模层（例如接触孔条纹和小焦点深度）相关联的问题，这可能导致短路或打开。

7. 发明申请

US20100308374A1 STRAINED CHANNEL TRANSISTOR STRUCTURE AND METHOD 有权
标题翻译：应变通道晶体管结构和方法
公开(公告)号：US20100308374A1
公开(公告)日：2010-12-09
申请号：US12857543
申请日：2010-08-16
申请人： Jin Ping LIU , Alex KH SEE , Mei Sheng ZHOU , Liang Choo HSIA
发明人： Jin Ping LIU , Alex KH SEE , Mei Sheng ZHOU , Liang Choo HSIA
IPC分类号： H01L29/78
CPC分类号： H01L29/7848 , H01L21/26506 , H01L29/165 , H01L29/66636
摘要： A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.
摘要翻译：一种晶体管器件结构，包括：由第一材料形成的衬底部分; 以及源区域，漏极区域和形成在所述衬底中的沟道区域，所述源极和漏极区域包括与所述第一材料不同的多个第二材料岛，所述岛被布置成在所述沟道区域中引起应变底物。

8. 发明申请

US20090146296A1 Method of forming high-k dielectric stop layer for contact hole opening 有权
标题翻译：形成用于接触孔开口的高k电介质停止层的方法
公开(公告)号：US20090146296A1
公开(公告)日：2009-06-11
申请号：US11953881
申请日：2007-12-11
申请人： Jianhui YE , Huang LIU , Alex KH SEE , Wei LU , Chun Hui LOW , Chim Seng SEET , Mei Sheng ZHOU , Liang Choo HSIA
发明人： Jianhui YE , Huang LIU , Alex KH SEE , Wei LU , Chun Hui LOW , Chim Seng SEET , Mei Sheng ZHOU , Liang Choo HSIA
IPC分类号： H01L21/461 , H01L23/48
CPC分类号： H01L21/76832 , H01L21/76895 , H01L21/76897
摘要： A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.
摘要翻译：包括初级和次级阻挡层的复合蚀刻停止层用于在电介质层中形成接触衬底中的区域的接触。次蚀刻停止层包括高k电介质材料，以在接触形成期间与电介质层实现高蚀刻选择性。去除次级停止层以暴露接触区域。通过对材料的高选择性实现二次停止层的去除。

9. 发明申请

US20100167505A1 METHODS FOR REDUCING LOADING EFFECTS DURING FILM FORMATION 有权
标题翻译：减少电影形成过程中负荷影响的方法
公开(公告)号：US20100167505A1
公开(公告)日：2010-07-01
申请号：US12648309
申请日：2009-12-29
申请人： Han Guan CHEW , Jinping LIU , Alex Kai Hung SEE , Mei Sheng ZHOU
发明人： Han Guan CHEW , Jinping LIU , Alex Kai Hung SEE , Mei Sheng ZHOU
IPC分类号： H01L21/20
CPC分类号： H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/823412 , H01L21/823418 , H01L29/7848
摘要： A method for fabricating a semiconductor device is provided. The method comprises selectively forming a first layer over a first and second exposed portions of a substrate. The first and second exposed portions are of different sizes and are located adjacent to a first and second active devices. During the first layer formation, a gas mixture comprising first and second source gases that function as growth components for forming the first layer and a reactant gas that functions as an etching component for controlling selectivity of the first layer growth is provided. The reactant gas is different from the first and second source gases and one of first and second source gases forms the first layer at a faster rate over the first exposed portion as compared to the second exposed portion and the other source gas exhibits an opposite behavior.
摘要翻译：提供一种制造半导体器件的方法。该方法包括在衬底的第一和第二暴露部分上选择性地形成第一层。第一和第二暴露部分具有不同的尺寸并且位于第一和第二有源器件附近。在第一层形成期间，提供了包含用作形成第一层的生长组分的第一和第二源气体和用作控制第一层生长选择性的蚀刻组分的反应气体的气体混合物。反应物气体与第一和第二源气体不同，并且第一和第二源气体之一与第二暴露部分相比以较快的速率在第一暴露部分上形成第一层，而另一个源气体表现出相反的作用。

10. 发明申请

US20090258445A1 MULTI-VARIABLE REGRESSION FOR METROLOGY 有权
标题翻译：多变量回归计量学
公开(公告)号：US20090258445A1
公开(公告)日：2009-10-15
申请号：US12103690
申请日：2008-04-15
申请人： Wen Zhan ZHOU , Zheng ZOU , Jasper GOH , Mei Sheng ZHOU
发明人： Wen Zhan ZHOU , Zheng ZOU , Jasper GOH , Mei Sheng ZHOU
IPC分类号： G01R35/00 , H01L21/66
CPC分类号： H01L22/12 , G01B21/045 , G01B2210/56 , H01L22/20
摘要： A method for assessing metrology tool accuracy is described. Multi-variable regression is used to define the accuracy of a metrology tool such that the interaction between different measurement parameters is taken into account. A metrology tool under test (MTUT) and a reference metrology tool (RMT) are used to measure a set of test profiles. The MTUT measures the test profiles to generate a MTUT data set for a first measurement parameter. The RMT measures the test profiles to generate RMT data sets for the first measurement parameter, and at least a second measurement parameter. Multi-variable regression is then performed to generate a best-fit plane for the data sets. The coefficient of determination (R2 value) represents the accuracy index of the MTUT.
摘要翻译：描述了一种评估测量工具精度的方法。多变量回归用于定义计量工具的准确性，以便考虑不同测量参数之间的相互作用。被测量的测量工具（MTUT）和参考计量工具（RMT）用于测量一组测试曲线。 MTUT测量测试配置文件，以生成第一个测量参数的MTUT数据集。 RMT测量测试配置文件以生成用于第一测量参数的RMT数据集和至少第二测量参数。然后执行多变量回归以为数据集生成最佳拟合平面。测定系数（R2值）表示MTUT的精度指标。

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