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1. 发明专利

JPH0474433A METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR INTERGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0474433A
公开(公告)日：1992-03-09
申请号：JP18821090
申请日：1990-07-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NISHIUMA MASAHIKO , KAMATA CHIYOSHI , MISHIMAGI HIROMITSU
IPC分类号： H01L21/60 , H01L21/321
摘要： PURPOSE:To remarkably enhance the connecting relaibility of an electrode to a bump electrode by a method wherein a metal foil is placed on the electrode on a mounting board, the electrode and the metal foil are heated and alloyed and the bump electrode is formed on the electrode. CONSTITUTION:An Au ribbon 11 is sucked and fixed onto a chuck block 35; a ribbon cutting blade 37 is lowered; the Au ribbon 11 is cut; an Au foil 12 having a prescribed area is formed. In succession, the foil is sucked by a chuck collet 39; it is conveyed to a metal-foil positioning part C; it is placed in the chip-mounting face of a package board 2. While the foil has been placed on a carrier 40, it is conveyed to a heating part D and is placed on a heating block 42. Then, in this state an electric current is applied to a heater 45 which has been built in the heating block 42; the package board 2 is heated to a prescribed temperature. Sn on the surface of electrodes 6 is diffused into the Au foil 12; a eutectic alloying reaction is caused; bump electrodes 7a which are composed of an Au-Sn alloy and which are in a molten state are formed on the respective electrodes 6 in a self-aligned manner. The residue of the Au foil 12 which has been sucked to a metal-foil fixation collet 43 is collected in a pocket 47; it is regenerated and utilized as the Au ribbon 11.

2. 发明专利

JPH06216272A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06216272A
公开(公告)日：1994-08-05
申请号：JP23215493
申请日：1993-09-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HARADA TAKU , YOSHIHARA KAZUHIRO , MASUZAWA KAZUTAKA , HAYASHI TERUYOSHI , KUMAZAWA ATSUSHI , NAGAI KENJI , NISHIUMA MASAHIKO , KAMATA CHIYOSHI
IPC分类号： H01L23/12 , H01L23/13 , H01L23/498 , H01L23/66
摘要： PURPOSE:To realize matching of characteristic impedance of signal transmitting lines in a package for mounting a semiconductor chip on which ultra-high speed LSI is formed. CONSTITUTION:One end of a signal transmitting line 203 formed on the main surface of a package substrate 204 is extended up to the area just under a pad formed on the main surface of a semiconductor chip 201 and is then electrically connected to a pad on a semiconductor chip 201 via a bump electrode. Moreover, the other end of the signal transmitting line 203 is extended up to the external circumference of the main surface of the package substrate 204 and is then coupled with an external lead 205.

3. 发明专利

JPH0412538A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0412538A
公开(公告)日：1992-01-17
申请号：JP11180890
申请日：1990-05-01
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： IMAI TOMIO , KAMATA CHIYOSHI
IPC分类号： H01L21/60
摘要： PURPOSE:To contrive a reduction in the size of a semiconductor device, whose leads are connected to the external terminals of a semiconductor chip, by a method wherein a conductor, to which a fixed potential is applied, is provided on the surface of each metal wiring interposing a dielectric between the metal wiring and the conductor. CONSTITUTION:A conductor 7c, to which a fixed potential is applied, is provided on the surface of each metal wire 7a interposing a dielectric 7b between the wire 7a and the conductor 7c. As a result, a parallel connection by-pass capacitor constituted using this metal wiring 7a connected with a lead wiring 4 for power supply use, to which a power supply is applied, as an electrode on one side and using the conductor 7c, to which the fixed potential is applied, as the other electrode can be formed within the occupation area of this metal wiring 7a. Thereby, the size of a package is reduced and a reduction in the size of a semiconductor device is contrived.

4. 发明专利

JPH0448756A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0448756A
公开(公告)日：1992-02-18
申请号：JP15522890
申请日：1990-06-15
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NISHIUMA MASAHIKO , KAMATA CHIYOSHI
IPC分类号： H01L23/12 , H01L21/60 , H01L23/49 , H01L23/64
摘要： PURPOSE:To bring the value of characteristic impedance of a bonding wire into coincidence with that of a signal line by disposing a constant potential metallized part near the wire for electrically connecting a semiconductor chip in an IC package to the line. CONSTITUTION:Since a GND metallized part 11a is disposed near a bonding wire 9 in an IC package 1 and an insulator 14 is interposed therebetween, the thickness of the insulator 14 (i.e., a distance between the part 11a and the wire 9) and the material i.e., relative permittivity) of the insulator 14 are suitably selected to bring the value of characteristic impedance of the wire 9 into coincidence with the value (50OMEGA) of the characteristic impedance of a signal line 7. Thus, since reflection of a signal, a waveform distortion in the package 1 are avoided, a high frequency signal can be transmitted without loss.

5. 发明专利

JPH0430544A INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0430544A
公开(公告)日：1992-02-03
申请号：JP13804890
申请日：1990-05-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NISHIUMA MASAHIKO , KAMATA CHIYOSHI
IPC分类号： H01L21/60 , H01L23/552
摘要： PURPOSE:To reduce crosstalk noise due to input/output signals carried by bump electrodes by providing a conductive member to surround individual bump electrodes on the surface of a chip, and maintain the conductive member at a constant potential. CONSTITUTION:A conductive member 7 is provided between a chip 2 and a printed-circuit board 1, and individual solder bumps 6 on the chip surface are surrounded with a gap by the conductive member 7. The conductive member is connected to an external constant potential source through internal wiring 4, and it shields the individual bumps. The gap between the conductive member and each bump is maintained at vacuum with a low dielectric constant. As a result, it is possible to reduce crosstalk noise due to input/output signals carried by the solder bumps 6. Therefore, the transfer characteristics of input/ output signals are improved, thereby preventing the malfunction of a logic IC on the chip 2.

6. 发明专利

JPH01293528A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01293528A
公开(公告)日：1989-11-27
申请号：JP12381288
申请日：1988-05-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： IMAI TOMIO , KAMATA CHIYOSHI , TSUBOI TOSHIHIRO
IPC分类号： H01L21/60 , H01L23/12
摘要： PURPOSE:To obtain a semiconductor device easy to perform impedance matching and of a structure suitable for very high speed operation, by connecting a semiconductor chip to a printed circuit board through a wiring block and other means. CONSTITUTION:A wiring block 2 having linear wirings arranged in parallel in a resin block is installed, the wirings of said wiring block 2 are connected with the pad of a semiconductor chip 1 through solder bumps 3, the connecting parts are covered by a chip coating material 4, and the semiconductor chip 1 and a part of the wiring block 2 are covered by sealing resin 5 to connect the semiconductor chip 1 with a printed circuit board 6 through the wiring block 2. For example, the wirings of said wiring block 2 include a wiring for a signal and a wiring for ground to match the impedance of said wiring for a signal and a pad for a signal and a pad for ground corresponding to said wirings are formed on the principal surface of said semiconductor chip 1.

7. 发明专利

JPH0823011A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0823011A
公开(公告)日：1996-01-23
申请号：JP15502994
申请日：1994-07-06
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： NISHIUMA MASAHIKO , SUWA MOTOHIRO , TAKAHASHI HIROYUKI , KAMATA CHIYOSHI
IPC分类号： H01L21/60 , H01L21/321
摘要： PURPOSE:To provide a semiconductor integrated circuit device, in which flip chip bonding can be carried out with high reliability, by detecting a defect in connection of a metallic bump easily. CONSTITUTION:An electrode connection gold bump 4 is formed on a mounting wiring board 2. A flip chip bonding step is carried out by using the electrode connection gold bump 4 to mount a semiconductor chip. At this time, a dummy gold bump 7 as high as the electrode connection gold bump 4 is formed near the semiconductor chip 6 on the mounting wiring board 2.

8. 发明专利

JPH06333982A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH06333982A
公开(公告)日：1994-12-02
申请号：JP11626693
申请日：1993-05-19
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUWA MOTOHIRO , TAKAHASHI HIROYUKI , NISHIUMA MASAHIKO , KAMATA CHIYOSHI
IPC分类号： H01L21/60 , H01L21/321 , H01L21/603
摘要： PURPOSE:To improve the reliability on connection between a semiconductor chip and a wiring board, in mounting technology of face down bonding a semiconductor chip on a wiring board. CONSTITUTION:This manufacture comprises a process of forming an Au ball 16 provided with an anchor part 17 having a pointed tip on the electrode pad 15 of a semiconductor chip 2, a process of forming an Au land 14 by flattening the Au ball junctioned on the electrode 5 of a wiring board 1, and a process of heating the Au ball 16 and the Au land 14, respectively, so as to soften them, and then, junctioning both by thermocompression bonding, and burying the anchor part 17 of the Au ball 16 in the Au land 14.

9. 发明专利

JPH03185900A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH03185900A
公开(公告)日：1991-08-13
申请号：JP32374589
申请日：1989-12-15
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： IMAI TOMIO , KAMATA CHIYOSHI
IPC分类号： H05K7/20 , H01L23/36 , H01L23/373 , H01L25/04 , H01L25/18
摘要： PURPOSE:To perform highly integrated packaging and high-efficiency cooling of an ingot simultaneously by a method wherein a wiring metal film is formed on the outer surface of the ingot formed into a polyhedron, a cylindrical body or a spherical body in a prescribed pattern and semiconductor chips, which are connected to the wiring metal film, are mounted on the outer surface of the ingot. CONSTITUTION:IC chips 2 are adhered on the whole periphery of the outer surface of a hollow and polyhedral silicon ingot 1 at prescribed arrangement intervals. The ingot 1 is arranged its external shape into a hexagonal pillar by a chamfering work, for example, and the outer diameter and height of the hexagonal pillar are respectively set in a dimension to correspond to a mounting density, but the diameter of a hollow part 3 is provided comparatively large for improving a cooling effect. The individual IC chips 2 are directly formed on the ingot 1 in the same method as the manufacturing method of normal semiconductor element. In case the member of the IC chips 2 is high and the IC chips are formed on the whole periphery of the ingot 1, the heat generation at the time of operation of the ingot becomes a considerable one. Then a cooling medium is circulated in the hollow of the ingot 1. Thereby, the cooling of the ingot is performed.

10. 发明专利

JPH02172249A JIG FOR INSPECTING PROBE 失效
公开(公告)号：JPH02172249A
公开(公告)日：1990-07-03
申请号：JP32584088
申请日：1988-12-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： IMAI TOMIO , KAMATA CHIYOSHI
IPC分类号： G01R31/28 , H01L21/66
摘要： PURPOSE:To prevent influence of noise caused by a transmission system connected to a probe by a method wherein signal transmission between the probe and respective inspection machines is performed by using optical fiber cables. CONSTITUTION:A plurality of optical fiber cables 1 are used, which are to be connected to inspection machines and an optic fiber cable connector 2 on a probe. Therefore, a signal from a signal generator or the like is output to the optical fiber 1, and an electric signal is supplied to a probe 5 for supplying signal with photoelectric conversion at its end 3 and printed on a specimen 11 to be inspected. On the other hand, an electric signal output from the specimen 11 is photoelectrically converted at a signal processing unit 4 immediately after it exits from the probe 5 for outputting, and the optical signal is applied to a measurement input unit of an inspection machine via the optical fiber 1. This enables signal transmission to be performed by optical signals so that the signal is completely free from influence of noise and measurement accuracy may not deteriorate.

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