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1. 发明授权

US08929376B2 Flow control using a local event ring in an island-based network flow processor 有权
标题翻译：在基于岛屿的网络流处理器中使用本地事件环的流控制
公开(公告)号：US08929376B2
公开(公告)日：2015-01-06
申请号：US13400008
申请日：2012-02-17
申请人： Gavin J. Stark , Steven W. Zagorianakos , Ron L. Swartzentruber , Richard P. Bouley
发明人： Gavin J. Stark , Steven W. Zagorianakos , Ron L. Swartzentruber , Richard P. Bouley
IPC分类号： H04L12/54 , G06F15/80
CPC分类号： H04L49/9047 , H04L47/13 , H04L49/102 , H04L49/9084
摘要： An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local event ring. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. The local event ring involves event ring circuits and event ring segments. In one example, a packet is received onto a first island. If an amount of a processing resource (for example, memory buffer space) available to the first island is below a threshold, then an event packet is communicated from the first island to a second island via the local event ring. In response, the second island causes a third island to communicate via a command/push/pull data bus with the first island, thereby increasing the amount of the processing resource available to the first island for handing incoming packets.
摘要翻译：基于岛屿的网络流处理器（IB-NFP）集成电路包括以行组织的岛屿。可配置的网状事件总线延伸穿过岛，并配置为形成本地事件环。配置的mesh事件总线配置有通过可配置的网状控制总线接收的配置信息。本地事件环包括事件环电路和事件环段。在一个示例中，分组被接收到第一岛上。如果第一岛可用的处理资源（例如，存储器缓冲空间）的量低于阈值，则事件分组通过本地事件环从第一岛传送到第二岛。作为响应，第二岛使得第三岛通过命令/推/拉数据总线与第一岛进行通信，从而增加第一岛可用于处理输入分组的处理资源的量。

2. 发明申请

US20130215901A1 Flow Control Using a Local Event Ring In An Island-Based Network Flow Processor 有权
标题翻译：在基于岛屿的网络流处理器中使用本地事件环的流控制
公开(公告)号：US20130215901A1
公开(公告)日：2013-08-22
申请号：US13400008
申请日：2012-02-17
申请人： Gavin J. Stark , Steven W. Zagorianakos , Ron L. Swartzentruber , Richard P. Bouley
发明人： Gavin J. Stark , Steven W. Zagorianakos , Ron L. Swartzentruber , Richard P. Bouley
IPC分类号： H04L12/56
CPC分类号： H04L49/9047 , H04L47/13 , H04L49/102 , H04L49/9084
摘要： An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local event ring. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. The local event ring involves event ring circuits and event ring segments. In one example, a packet is received onto a first island. If an amount of a processing resource (for example, memory buffer space) available to the first island is below a threshold, then an event packet is communicated from the first island to a second island via the local event ring. In response, the second island causes a third island to communicate via a command/push/pull data bus with the first island, thereby increasing the amount of the processing resource available to the first island for handing incoming packets.
摘要翻译：基于岛屿的网络流处理器（IB-NFP）集成电路包括以行组织的岛屿。可配置的网状事件总线延伸穿过岛，并配置为形成本地事件环。配置的mesh事件总线配置有通过可配置的网状控制总线接收的配置信息。本地事件环包括事件环电路和事件环段。在一个示例中，分组被接收到第一岛上。如果第一岛可用的处理资源（例如，存储器缓冲空间）的量低于阈值，则事件分组通过本地事件环从第一岛传送到第二岛。作为响应，第二岛使得第三岛通过命令/推/拉数据总线与第一岛进行通信，从而增加第一岛可用于处理输入分组的处理资源的量。

3. 发明授权

US08559436B2 Processing resource management in an island-based network flow processor 有权
标题翻译：在基于岛屿的网络流处理器中处理资源管理
公开(公告)号：US08559436B2
公开(公告)日：2013-10-15
申请号：US13399958
申请日：2012-02-17
申请人： Gavin J. Stark , Steven W. Zagorianakos , Ron L. Swartzentruber
发明人： Gavin J. Stark , Steven W. Zagorianakos , Ron L. Swartzentruber
IPC分类号： H04L12/28 , H04L12/54 , G06F15/173
CPC分类号： H04L12/6418
摘要： An island-based network flow processor (IB-NFP) integrated circuit has a high performance processor island. The processor island has a processor and a tightly coupled memory. The integrated circuit also has another memory. The other memory may be internal or external memory. The header of an incoming packet is stored in the tightly coupled memory of the processor island. The payload is stored in the other memory. In one example, if the amount of a processing resource is below a threshold then the header is moved from the first island to the other memory before the header and payload are communicated to an egress island for outputting from the integrated circuit. If, however, the amount of the processing resource is not below the threshold then the header is moved directly from the processor island to the egress island and is combined with the payload there for outputting from the integrated circuit.
摘要翻译：基于岛屿的网络流处理器（IB-NFP）集成电路具有高性能的处理器岛。处理器岛具有处理器和紧耦合的存储器。该集成电路还具有另一个存储器。其他内存可能是内部或外部存储器。输入分组的报头被存储在处理器岛的紧耦合存储器中。有效载荷存储在另一个存储器中。在一个示例中，如果处理资源的量低于阈值，则在首标和有效载荷被传送到出口岛以从集成电路输出之前，首标从第一岛移动到另一个存储器。然而，如果处理资源的数量不低于阈值，则标题直接从处理器岛移动到出口岛，并且与有效载荷组合以从集成电路输出。

4. 发明申请

US20130215893A1 Processing Resource Management In An Island-Based Network Flow Processor 有权
标题翻译：在基于岛屿的网络流处理器中处理资源管理
公开(公告)号：US20130215893A1
公开(公告)日：2013-08-22
申请号：US13399958
申请日：2012-02-17
申请人： Gavin J. Stark , Steven W. Zagorianakos , Ron L. Swartzentruber
发明人： Gavin J. Stark , Steven W. Zagorianakos , Ron L. Swartzentruber
IPC分类号： H04L12/56
CPC分类号： H04L12/6418
摘要： An island-based network flow processor (IB-NFP) integrated circuit has a high performance processor island. The processor island has a processor and a tightly coupled memory. The integrated circuit also has another memory. The other memory may be internal or external memory. The header of an incoming packet is stored in the tightly coupled memory of the processor island. The payload is stored in the other memory. In one example, if the amount of a processing resource is below a threshold then the header is moved from the first island to the other memory before the header and payload are communicated to an egress island for outputting from the integrated circuit. If, however, the amount of the processing resource is not below the threshold then the header is moved directly from the processor island to the egress island and is combined with the payload there for outputting from the integrated circuit.
摘要翻译：基于岛屿的网络流处理器（IB-NFP）集成电路具有高性能的处理器岛。处理器岛具有处理器和紧耦合的存储器。该集成电路还具有另一个存储器。其他内存可能是内部或外部存储器。输入分组的报头被存储在处理器岛的紧耦合存储器中。有效载荷存储在另一个存储器中。在一个示例中，如果处理资源的量低于阈值，则在首标和有效载荷被传送到出口岛以从集成电路输出之前，首标从第一岛移动到另一个存储器。然而，如果处理资源的数量不低于阈值，则标题直接从处理器岛移动到出口岛，并且与有效载荷组合以从集成电路输出。

5. 发明申请

US20140025918A1 Transactional Memory that Performs a Direct 32-bit Lookup Operation 有权
标题翻译：执行直接32位查找操作的事务内存
公开(公告)号：US20140025918A1
公开(公告)日：2014-01-23
申请号：US13552605
申请日：2012-07-18
申请人： Gavin J. Stark , Ron L. Swartzentruber
发明人： Gavin J. Stark , Ron L. Swartzentruber
IPC分类号： G06F12/10
CPC分类号： H04L12/4625 , G06F9/3004 , G06F12/06 , G06F15/163
摘要： A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a base address, a starting bit position, and a mask size. In response to the lookup command, the TM pulls an input value (IV). The TM uses the starting bit position and the mask size to select a portion of the IV. A first sub-portion of the portion of the IV and the base address are summed to generate a memory address. The memory address is used to read a word containing multiple result values (RVs) from memory. One RV from the word is selected using a multiplexing circuit and a second sub-portion of the portion of the IV. If the selected RV is a final value, then lookup operation is complete and the TM sends the RV to the processor, otherwise the TM performs another lookup operation based upon the selected RV.
摘要翻译：事务存储器（TM）从处理器接收总线上的查找命令。该命令包括基地址，起始位位置和掩码大小。响应于查找命令，TM拉取输入值（IV）。 TM使用起始位位置和掩码大小来选择IV的一部分。将IV的部分和基地址的第一子部分相加以生成存储器地址。存储器地址用于从存储器读取包含多个结果值（RV）的单词。使用多路复用电路和IV部分的第二子部分选择来自该单词的一个RV。如果所选的RV是最终值，则查找操作完成，并且TM将RV发送到处理器，否则TM基于所选择的RV执行另一查找操作。

6. 发明授权

US09100212B2 Transactional memory that performs a direct 32-bit lookup operation 有权
标题翻译：执行直接32位查找操作的事务内存
公开(公告)号：US09100212B2
公开(公告)日：2015-08-04
申请号：US13552605
申请日：2012-07-18
申请人： Gavin J. Stark , Ron L. Swartzentruber
发明人： Gavin J. Stark , Ron L. Swartzentruber
IPC分类号： G06F12/00 , H04L12/46 , G06F12/06 , G06F9/30 , G06F15/163
CPC分类号： H04L12/4625 , G06F9/3004 , G06F12/06 , G06F15/163
摘要： A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a base address, a starting bit position, and a mask size. In response to the lookup command, the TM pulls an input value (IV). The TM uses the starting bit position and the mask size to select a portion of the IV. A first sub-portion of the portion of the IV and the base address are summed to generate a memory address. The memory address is used to read a word containing multiple result values (RVs) from memory. One RV from the word is selected using a multiplexing circuit and a second sub-portion of the portion of the IV. If the selected RV is a final value, then lookup operation is complete and the TM sends the RV to the processor, otherwise the TM performs another lookup operation based upon the selected RV.
摘要翻译：事务存储器（TM）从处理器接收总线上的查找命令。该命令包括基地址，起始位位置和掩码大小。响应于查找命令，TM拉取输入值（IV）。 TM使用起始位位置和掩码大小来选择IV的一部分。将IV的部分和基地址的第一子部分相加以生成存储器地址。存储器地址用于从存储器读取包含多个结果值（RV）的单词。使用多路复用电路和IV部分的第二子部分选择来自该单词的一个RV。如果所选的RV是最终值，则查找操作完成，并且TM将RV发送到处理器，否则TM基于所选择的RV执行另一查找操作。

7. 发明授权

US09069649B2 Distributed credit FIFO link of a configurable mesh data bus 有权
标题翻译：可配置的网状数据总线的分布式信用FIFO链路
公开(公告)号：US09069649B2
公开(公告)日：2015-06-30
申请号：US13399846
申请日：2012-02-17
申请人： Gavin J. Stark , Steven W. Zagorianakos , Ronald N. Fortino
发明人： Gavin J. Stark , Steven W. Zagorianakos , Ronald N. Fortino
IPC分类号： G06F13/00 , H04L12/801 , H04L12/879
CPC分类号： G06F13/4022 , G06F13/00 , H04L47/39 , H04L49/901
摘要： An island-based integrated circuit includes a configurable mesh data bus. The data bus includes four meshes. Each mesh includes, for each island, a crossbar switch and radiating half links. The half links of adjacent islands align to form links between crossbar switches. A link is implemented as two distributed credit FIFOs. In one direction, a link portion involves a FIFO associated with an output port of a first island, a first chain of registers, and a second FIFO associated with an input port of a second island. When a transaction value passes through the FIFO and through the crossbar switch of the second island, an arbiter in the crossbar switch returns a taken signal. The taken signal passes back through a second chain of registers to a credit count circuit in the first island. The credit count circuit maintains a credit count value for the distributed credit FIFO.
摘要翻译：基于岛的集成电路包括可配置的网状数据总线。数据总线包括四个网格。每个网格对于每个岛包括一个交叉开关和辐射半连接。相邻岛屿的半连接对齐以形成交叉开关之间的连接。链接被实现为两个分布式信用FIFO。在一个方向上，链接部分涉及与第一岛的输出端口，第一寄存器链和与第二岛的输入端口相关联的第二FIFO相关联的FIFO。当交易值通过FIFO并通过第二岛的交叉开关时，交叉开关中的仲裁器返回一个取得的信号。所采集的信号通过第二个寄存器链回到第一个岛的信用计数电路。信用计数电路维持分配信用FIFO的信用计数值。

8. 发明申请

US20130219094A1 Commonality of Memory Island Interface and Structure 有权
标题翻译：内存岛接口和结构的共性
公开(公告)号：US20130219094A1
公开(公告)日：2013-08-22
申请号：US13399915
申请日：2012-02-17
申请人： Gavin J. Stark , Steven W. Zagorianakos
发明人： Gavin J. Stark , Steven W. Zagorianakos
IPC分类号： G06F13/20
CPC分类号： G06F13/20 , G06F13/385
摘要： The functional circuitry of a network flow processor is partitioned into a number of rectangular islands. The islands are disposed in rows. A configurable mesh data bus extends through the islands. A first island includes a first memory and a first data bus interface. A second island includes a processor, a second memory, and a second data bus interface. The processor can issue a command for a target memory to do an action. If a field in the command has a first value then the target memory is the first memory, whereas if the field has a second value then the target memory is in the second memory. The command format is the same, regardless of whether the target memory is local or remote. If the target memory is remote, then a data bus bridge adds destination information before putting the command onto the global configurable mesh data bus.
摘要翻译：网络流处理器的功能电路被划分成多个矩形岛。这些岛屿排列成行。可配置的网状数据总线延伸穿过岛。第一岛包括第一存储器和第一数据总线接口。第二岛包括处理器，第二存储器和第二数据总线接口。处理器可以为目标内存发出一个命令来执行一个动作。如果命令中的字段具有第一个值，则目标存储器是第一个存储器，而如果该字段具有第二个值，则目标存储器位于第二个存储器中。命令格式相同，无论目标内存是本地还是远程目标内存。如果目标存储器是远程的，则在将命令放入全局可配置的网格数据总线之前，数据总线桥接器将添加目标信息。

9. 发明授权

US09405713B2 Commonality of memory island interface and structure 有权
标题翻译：记忆岛界面和结构的共性
公开(公告)号：US09405713B2
公开(公告)日：2016-08-02
申请号：US13399915
申请日：2012-02-17
申请人： Gavin J. Stark , Steven W. Zagorianakos
发明人： Gavin J. Stark , Steven W. Zagorianakos
IPC分类号： G06F13/00 , G06F13/20
CPC分类号： G06F13/20 , G06F13/385
摘要： The functional circuitry of a network flow processor is partitioned into a number of rectangular islands. The islands are disposed in rows. A configurable mesh data bus extends through the islands. A first island includes a first memory and a first data bus interface. A second island includes a processor, a second memory, and a second data bus interface. The processor can issue a command for a target memory to do an action. If a field in the command has a first value then the target memory is the first memory, whereas if the field has a second value then the target memory is in the second memory. The command format is the same, regardless of whether the target memory is local or remote. If the target memory is remote, then a data bus bridge adds destination information before putting the command onto the global configurable mesh data bus.
摘要翻译：网络流处理器的功能电路被划分成多个矩形岛。这些岛屿排列成行。可配置的网状数据总线延伸穿过岛。第一岛包括第一存储器和第一数据总线接口。第二岛包括处理器，第二存储器和第二数据总线接口。处理器可以为目标内存发出一个命令来执行一个动作。如果命令中的字段具有第一个值，则目标存储器是第一个存储器，而如果该字段具有第二个值，则目标存储器位于第二个存储器中。命令格式相同，无论目标内存是本地还是远程目标内存。如果目标存储器是远程的，则在将命令放入全局可配置的网格数据总线之前，数据总线桥接器将添加目标信息。

10. 发明授权

US09237095B2 Island-based network flow processor integrated circuit 有权
标题翻译：基于岛屿的网络流处理器集成电路
公开(公告)号：US09237095B2
公开(公告)日：2016-01-12
申请号：US13399888
申请日：2012-02-17
申请人： Gavin J. Stark , Steven W. Zagorianakos
发明人： Gavin J. Stark , Steven W. Zagorianakos
IPC分类号： G06F13/00 , H04L12/723 , G06F15/78
CPC分类号： H04L45/50 , G06F15/7867 , Y10T29/49124
摘要： A reconfigurable, scalable and flexible island-based network flow processor integrated circuit architecture includes a plurality of rectangular islands of identical shape and size. The islands are disposed in rows, and a configurable mesh command/push/pull data bus extends through all the islands. The integrated circuit includes first SerDes I/O blocks, an ingress MAC island that converts incoming symbols into packets, an ingress NBI island that analyzes packets and generates ingress packet descriptors, a microengine (ME) island that receives ingress packet descriptors and headers from the ingress NBI and analyzes the headers, a memory unit (MU) island that receives payloads from the ingress NBI and performs lookup operations and stores payloads, an egress NBI island that receives the header portions and the payload portions and egress descriptors and performs egress scheduling, and an egress MAC island that outputs packets to second SerDes I/O blocks.
摘要翻译：可重构，可扩展和灵活的基于岛的网络流处理器集成电路架构包括多个相同形状和大小的矩形岛。岛排列成行，并且可配置的网格命令/推/拉数据总线延伸穿过所有岛。该集成电路包括第一个SerDes I / O块，一个将输入符号转换成数据包的入口MAC岛，一个分析数据包并产生入口包描述符的入口NBI岛，一个微型引擎（ME）岛，接收入口数据包描述符和头入口NBI并分析头部，存储单元（MU）岛，其从入口NBI接收有效载荷并执行查找操作并存储有效载荷;接收标题部分和有效载荷部分和出口描述符并执行出口调度的出口NBI岛，以及向第二SerDes I / O块输出数据包的出口MAC岛。

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