专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP2973756B1 NANOWIRE LED STRUCTURE WITH DECREASED LEAKAGE AND METHOD OF MAKING SAME 有权
公开(公告)号：EP2973756B1
公开(公告)日：2018-06-27
申请号：EP14762216.1
申请日：2014-03-14
申请人： GLO AB , Svensson, Carl Patrik Theodor , Romano, Linda , Herner, Scott Brad , Lemay, Cynthia
发明人： SVENSSON, Carl Patrik Theodor , ROMANO, Linda , HERNER, Scott Brad , LEMAY, Cynthia
IPC分类号： H01L33/24 , H01L33/00
CPC分类号： H01L33/24 , B82Y20/00 , H01L33/007 , Y10S977/762 , Y10S977/95
摘要： A semiconductor device includes a plurality of first conductivity type semiconductor nanowire cores located over a support, and an insulating mask layer located over the support. The nanowire cores include semiconductor nanowires epitaxially extending from portions of a semiconductor surface of the support exposed through openings in the insulating mask layer. The device also includes a plurality of second conductivity type semiconductor shells extending over and around the respective nanowire cores, a first electrode layer that contacts the second conductivity type semiconductor shells and extends into spaces between the semiconductor shells, and an insulating layer located between the insulating mask layer and the first electrode in the spaces between the semiconductor shells.

2. 发明公开

EP2973756A1 NANOWIRE LED STRUCTURE WITH DECREASED LEAKAGE AND METHOD OF MAKING SAME 有权
标题翻译： NANODRAHT-LED-STRUKTUR MIT VERMINDERTER LECKAGE UND VERFAHREN ZUR HERSTELLUNG DAVON
公开(公告)号：EP2973756A1
公开(公告)日：2016-01-20
申请号：EP14762216.1
申请日：2014-03-14
申请人： GLO AB , Svensson, Carl Patrik Theodor , Romano, Linda , Herner, Scott Brad , Lemay, Cynthia
发明人： SVENSSON, Carl Patrik Theodor , ROMANO, Linda , HERNER, Scott Brad , LEMAY, Cynthia
IPC分类号： H01L33/20
CPC分类号： H01L33/24 , B82Y20/00 , H01L33/007 , Y10S977/762 , Y10S977/95
摘要： A semiconductor device includes a plurality of first conductivity type semiconductor nanowire cores extending from portions of a surface of a support exposed through openings in a mask layer, and a plurality of semiconductor shells extending over the nanowire cores. Each semiconductor shell includes at least one semiconductor interior shell extending around the respective nanowire cores, and a second conductivity type semiconductor outer shell extending around the interior shell. A first electrode layer contacts the second conductivity type semiconductor outer shell and extends into spaces between the semiconductor shells. The semiconductor interior shell includes a semiconductor foot portion which extends under the first electrode and under the respective second conductivity type semiconductor outer shell on the insulating masking layer in the spaces between the semiconductor shells. Semiconductor devices and methods including an insulating layer located between an insulating mask layer and a first electrode in the spaces between semiconductor shells.
摘要翻译：半导体器件包括位于支撑体上方的多个第一导电型半导体纳米线芯，以及位于支撑体上方的绝缘掩模层。纳米线芯包括从通过绝缘掩模层中的开口露出的支撑体的半导体表面的部分外延延伸的半导体纳米线。该器件还包括在相应的纳米线芯之上和之上延伸的多个第二导电类型半导体外壳，与第二导电类型半导体外壳接触并延伸到半导体外壳之间的空间的第一电极层，以及位于绝缘层之间的绝缘层掩模层和半导体外壳之间的空间中的第一电极。

3. 发明申请

WO2014143991A1 NANOWIRE LED STRUCTURE WITH DECREASED LEAKAGE AND METHOD OF MAKING SAME 审中-公开
标题翻译： NANOWIRE LED结构具有减少的泄漏及其制造方法
公开(公告)号：WO2014143991A1
公开(公告)日：2014-09-18
申请号：PCT/US2014/028208
申请日：2014-03-14
申请人： GLO AB , SVENSSON, Carl Patrik Theodor , ROMANO, Linda , HERNER, Scott Brad , LEMAY, Cynthia
发明人： SVENSSON, Carl Patrik Theodor , ROMANO, Linda , HERNER, Scott Brad , LEMAY, Cynthia
IPC分类号： H01L33/20
CPC分类号： H01L33/24 , B82Y20/00 , H01L33/007 , Y10S977/762 , Y10S977/95
摘要： A semiconductor device includes a plurality of first conductivity type semiconductor nanowire cores extending from portions of a surface of a support exposed through openings in a mask layer, and a plurality of semiconductor shells extending over the nanowire cores. Each semiconductor shell includes at least one semiconductor interior shell extending around the respective nanowire cores, and a second conductivity type semiconductor outer shell extending around the interior shell. A first electrode layer contacts the second conductivity type semiconductor outer shell and extends into spaces between the semiconductor shells. The semiconductor interior shell includes a semiconductor foot portion which extends under the first electrode and under the respective second conductivity type semiconductor outer shell on the insulating masking layer in the spaces between the semiconductor shells. Semiconductor devices and methods including an insulating layer located between an insulating mask layer and a first electrode in the spaces between semiconductor shells.
摘要翻译：半导体器件包括从通过掩模层中的开口暴露的支撑体的表面的部分延伸的多个第一导电型半导体纳米线芯，以及在纳米线芯上延伸的多个半导体外壳。每个半导体外壳包括围绕相应的纳米线芯延伸的至少一个半导体内壳，以及围绕内壳延伸的第二导电型半导体外壳。第一电极层接触第二导电类型半导体外壳并延伸到半导体外壳之间的空间。半导体内壳包括在半导体外壳之间的空间中在绝缘屏蔽层下方延伸在第一电极下方和相应的第二导电类型半导体外壳下方的半导体底座部分。半导体器件和方法包括位于半导体外壳之间的绝缘掩模层和第一电极之间的绝缘层。

4. 发明申请

WO2015077612A1 METHOD OF STRESS INDUCED CLEAVING OF SEMICONDUCTOR DEVICES 审中-公开
标题翻译：应力诱导半导体器件的清除方法
公开(公告)号：WO2015077612A1
公开(公告)日：2015-05-28
申请号：PCT/US2014/066899
申请日：2014-11-21
申请人： GLO AB , HERNER, Scott Brad , ROMANO, Linda , THOMPSON, Daniel Bryce , SCHUBERT, Martin
发明人： HERNER, Scott Brad , ROMANO, Linda , THOMPSON, Daniel Bryce , SCHUBERT, Martin
IPC分类号： H01L33/00 , H01L21/78 , H01L21/30
CPC分类号： H01L33/0095 , B23K26/0057 , B23K26/40 , B23K26/402 , B23K26/53 , H01L33/20
摘要： A method of dicing semiconductor devices includes depositing a continuous first layer over the substrate, such that the first layer imparts a compressive stress to the substrate, and etching grooves in the first layer to increase local stress at the grooves compared to stress at the remainder of the first layer located over the substrate. The method also includes generating a pattern of defects in the substrate with a laser beam, such that a location of the defects in the pattern of defects substantially corresponds to a location of at least some of the grooves in the in the first layer, and applying pressure to the substrate to dice the substrate along the grooves.
摘要翻译：一种切割半导体器件的方法包括在衬底上沉积连续的第一层，使得第一层向衬底施加压缩应力，并且在第一层中蚀刻凹槽以增加沟槽处的局部应力，与其余部分的应力相比第一层位于衬底上。该方法还包括用激光束产生衬底中的缺陷图案，使得缺陷图案中的缺陷位置基本上对应于第一层中的至少一些凹槽的位置，以及施加对基板的压力沿着凹槽切割基板。

5. 发明申请

WO2015077609A1 METHODS OF LOCATING DIFFERENTLY SHAPED OR DIFFERENTLY SIZED LED DIE IN A SUBMOUNT 审中-公开
标题翻译：在不同形状或不同尺寸的LED模具中定位的方法
公开(公告)号：WO2015077609A1
公开(公告)日：2015-05-28
申请号：PCT/US2014/066894
申请日：2014-11-21
申请人： GLO AB , HERNER, Scott Brad , ROMANO, Linda , THOMPSON, Daniel Bryce , SCHUBERT, Martin , KANESHIRO, Ronald
发明人： HERNER, Scott Brad , ROMANO, Linda , THOMPSON, Daniel Bryce , SCHUBERT, Martin , KANESHIRO, Ronald
IPC分类号： F21S2/00
CPC分类号： H01L33/483 , G02B19/0066 , H01L27/153 , H01L33/0095 , H01L33/20 , H01L33/32 , H01L2224/45144 , H01L2224/48227 , H01L2933/0033 , H01L2924/00
摘要： Methods of locating a plurality of light emitting diode (LED) dies in a submount include providing the plurality of LED dies across a surface of the submount, the submount including a plurality of tubs corresponding in shape and/or size with the shape and/or size of the LED dies to fill each tub with correspondingly shaped and/or sized LED die.
摘要翻译：将多个发光二极管（LED）裸片定位在基座中的方法包括：在多个基座的表面上设置多个LED管芯，该底座包括形状和/或尺寸对应的多个与形状和/或尺寸形状和/ LED的尺寸为相应形状和/或尺寸的LED管芯填充每个桶。

6. 发明申请

WO2015077623A1 LED SUBMOUNT WITH INTEGRATED INTERCONNECTS 审中-公开
标题翻译：具有集成互连的LED电源
公开(公告)号：WO2015077623A1
公开(公告)日：2015-05-28
申请号：PCT/US2014/066919
申请日：2014-11-21
申请人： GLO AB , HERNER, Scott Brad , ROMANO, Linda , THOMPSON, Daniel Bryce , SCHUBERT, Martin
发明人： HERNER, Scott Brad , ROMANO, Linda , THOMPSON, Daniel Bryce , SCHUBERT, Martin
IPC分类号： H01L33/62
CPC分类号： H01L33/486 , H01L27/156 , H01L33/0095 , H01L33/20 , H01L33/62 , H01L2224/45144 , H01L2224/48091 , H01L2224/48464 , H01L2224/73265 , H01L2933/0033 , H01L2933/0066 , H01L2924/00014 , H01L2924/00
摘要： A submount for light emitting diode (LED) die includes a substrate containing a plurality of tubs configured to receive an LED die, and a plurality of integrated interconnects integrated into the substrate. At least a portion of the interconnects for each tub have an exposed portion on a side of the submount and at least some of the plurality of the interconnects are not connected to other interconnects in the submount.
摘要翻译：发光二极管（LED）裸片的基座包括：衬底，其包含被构造成接收LED管芯的多个槽，以及集成到衬底中的多个集成互连。每个桶的互连的至少一部分具有在基座的一侧上的暴露部分，并且多个互连中的至少一些不连接到副安装座中的其它互连。

7. 发明申请

WO2016025325A1 III-NITRIDE NANOWIRE LED WITH STRAIN MODIFIED SURFACE ACTIVE REGION AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：具有应变改性表面活性区域的III-NITRIDE NANOWIRE LED及其制备方法
公开(公告)号：WO2016025325A1
公开(公告)日：2016-02-18
申请号：PCT/US2015/044245
申请日：2015-08-07
申请人： GLO AB , ROMANO, Linda , WANG, Ping
发明人： ROMANO, Linda , WANG, Ping
IPC分类号： H01L33/02 , H01L33/26
CPC分类号： H01L33/24 , H01L33/007 , H01L33/025 , H01L33/06 , H01L33/08 , H01L33/12 , H01L33/18 , H01L33/32 , H01L33/42
摘要： A core- shell nanowire device includes an eave region having a structural discontinuity from the p-plane in the upper tip portion of the shell to the m-plane in the lower portion of the shell. The eave region has at least 5 atomic percent higher indium content than the p-plane and m-plane portions of the shell.
摘要翻译：核 - 壳纳米线装置包括檐部区域，其具有从壳体的上端部中的p平面到壳体下部中的m平面的结构不连续性。檐区具有比壳的p面和m面部分高至少5原子％的铟含量。

8. 发明申请

WO2015095049A1 III-NITRIDE NANOWIRE LED WITH STRAIN MODIFIED SURFACE ACTIVE REGION AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：具有应变改性表面活性区域的III-NITRIDE NANOWIRE LED及其制备方法
公开(公告)号：WO2015095049A1
公开(公告)日：2015-06-25
申请号：PCT/US2014/070347
申请日：2014-12-15
申请人： GLO AB , ROMANO, Linda , YI, Sungsoo , SVENSSON, Patrik , GARDNER, Nathan
发明人： ROMANO, Linda , YI, Sungsoo , SVENSSON, Patrik , GARDNER, Nathan
IPC分类号： H01L33/20
CPC分类号： H01L33/06 , H01L27/15 , H01L27/153 , H01L33/0025 , H01L33/0075 , H01L33/12 , H01L33/20 , H01L33/22 , H01L33/24 , H01L33/32 , H01L33/42 , H01L2933/0016
摘要： A light emitting diode (LED) device includes a semiconductor nanowire core, and an In(Al)GaN active region quantum well shell located radially around the semiconductor nanowire core. The active quantum well shell contains indium rich regions having at least 5 atomic percent higher indium content than indium poor regions in the same shell. The active region quantum well shell has a non-uniform surface profile having at least 3 peaks. Each of the at least 3 peaks is separated from an adjacent one of the at least 3 peaks by a valley, and each of the at least 3 peaks extends at least 2 nm in a radial direction away from an adjacent valley.
摘要翻译：发光二极管（LED）器件包括半导体纳米线芯和位于半导体纳米线芯径向周围的In（Al）GaN有源区量子阱壳。有源量子阱壳含有富铟区，铟含量比同一壳中的铟贫区高至少5原子％。有源区域量子阱壳具有至少3个峰的不均匀表面轮廓。所述至少3个峰中的每一个与所述至少3个峰中的相邻的一个峰分开一个谷，并且所述至少3个峰中的每一个在远离相邻谷的径向方向上延伸至少2nm。

9. 发明申请

WO2013020051A1 METHOD AND SYSTEM FOR A GAN VERTICAL JFET UTILIZING A REGROWN CHANNEL 审中-公开
标题翻译：用于使用注册通道的GAN垂直JFET的方法和系统
公开(公告)号：WO2013020051A1
公开(公告)日：2013-02-07
申请号：PCT/US2012/049520
申请日：2012-08-03
申请人： AVOGY, INC. , KIZILYALLI, Isik C. , NIE, Hui , EDWARDS, Andrew P. , ROMANO, Linda , BOUR, David P. , BROWN, Richard J. , PRUNTY, Thomas R.
发明人： KIZILYALLI, Isik C. , NIE, Hui , EDWARDS, Andrew P. , ROMANO, Linda , BOUR, David P. , BROWN, Richard J. , PRUNTY, Thomas R.
IPC分类号： H01L29/772
CPC分类号： H01L29/66909 , H01L21/8252 , H01L27/0605 , H01L29/1066 , H01L29/2003 , H01L29/66446 , H01L29/66924 , H01L29/8083
摘要： A vertical Ill-nitride field effect transistor includes a drain comprising a first Ill-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second Ill-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third Ill-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical Ill-nitride field effect transistor is along the vertical direction, and the channel region extends along at least a portion of the second surface of the gate region.
摘要翻译：垂直III族氮化物场效应晶体管包括：包括第一III族氮化物材料的漏极，与漏极电耦合的漏极接触点，以及包括耦合到漏极的第二III族氮化物材料的漂移区域。场效应晶体管还包括沟道区，该沟道区包括耦合到漏极并沿着垂直方向邻近漏极设置的第三III族氮化物材料，至少部分围绕沟道区的栅极区。场效应晶体管还包括耦合到沟道区的源极和电耦合到源极的源极接触。沟道区域沿着垂直方向设置在漏极和源极之间，使得垂直的氮化物场效应晶体管的工作期间的电流沿着垂直方向，并且沟道区沿第二表面的至少一部分延伸的门区域。

10. 发明申请

WO2013055631A1 SCHOTTKY DIODE WITH BURIED LAYER IN GAN MATERIALS 审中-公开
标题翻译：肖特基二极管与煤炭材料中的包层
公开(公告)号：WO2013055631A1
公开(公告)日：2013-04-18
申请号：PCT/US2012/059250
申请日：2012-10-08
申请人： AVOGY, INC. , EDWARDS, Andrew, P. , NIE, Hui , KIZILYALLI, Isik, C. , BROWN, Richard, J. , BOUR, David, P. , ROMANO, Linda , PRUNTY, Thomas, R.
发明人： EDWARDS, Andrew, P. , NIE, Hui , KIZILYALLI, Isik, C. , BROWN, Richard, J. , BOUR, David, P. , ROMANO, Linda , PRUNTY, Thomas, R.
IPC分类号： H01L29/20
CPC分类号： H01L29/66143 , H01L21/26546 , H01L29/0615 , H01L29/0619 , H01L29/0692 , H01L29/08 , H01L29/2003 , H01L29/404 , H01L29/66083 , H01L29/66204 , H01L29/66212 , H01L29/66416 , H01L29/66924 , H01L29/8083 , H01L29/868 , H01L29/872
摘要： A semiconductor structure includes a III-nitride substrate characterized by a first conductivity type and having a first side and a second side opposing the first side, a III-nitride epitaxial layer of the first conductivity type coupled to the first side of the III-nitride substrate, and a plurality of III-nitride epitaxial structures of a second conductivity type coupled to the III-nitride epitaxial layer. The semiconductor structure further includes a III-nitride epitaxial formation of the first conductivity type coupled to the plurality of III-nitride epitaxial structures, and a metallic structure forming a Schottky contact with the III-nitride epitaxial formation and coupled to at least one of the plurality of III-nitride epitaxial structures.
摘要翻译：半导体结构包括III族氮化物衬底，其特征在于具有第一导电类型并且具有与第一侧相对的第一侧和第二侧，第一导电类型的III族氮化物外延层耦合到III族氮化物的第一侧衬底以及耦合到III族氮化物外延层的第二导电类型的多个III族氮化物外延结构。半导体结构还包括耦合到多个III族氮化物外延结构的第一导电类型的III族氮化物外延形成，以及形成与III族氮化物外延形成肖特基接触的金属结构，并与多个III族氮化物外延结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式