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1. 发明申请

US20190123206A1 OXIDE THIN FILM TRANSISTOR DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE 审中-公开
公开(公告)号：US20190123206A1
公开(公告)日：2019-04-25
申请号：US15971089
申请日：2018-05-04
申请人： BOE TECHNOLOGY GROUP CO., LTD. , FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
发明人： Xiaowei LIU , Fanqing MENG , Yang WANG , Yabin AN , Zhiyong FAN , Chenglong WU
IPC分类号： H01L29/786 , H01L27/12 , G02F1/1362 , G02F1/1368
摘要： The present disclosure provides in some embodiments an oxide TFT display substrate, a manufacture method thereof and a display device. The oxide TFT display substrate includes a first region at least corresponding to a semiconducting region of an oxide TFT and a second region other than the first region. The method includes steps of: forming, after the formation of the oxide TFT, a SiON layer at least covering the first region; and forming a SiNx layer covering the second region.

2. 发明申请

US20190097058A1 OXIDE THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE 审中-公开
公开(公告)号：US20190097058A1
公开(公告)日：2019-03-28
申请号：US15995706
申请日：2018-06-01
申请人： BOE TECHNOLOGY GROUP CO., LTD. , FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
发明人： Xiaowei LIU , Bo LIU , Yang WANG , Liangliang LI , Zheng LIU , Hongjiang WU , Jianfeng YUAN
IPC分类号： H01L29/786 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/66
摘要： Embodiments of the present application provide an Oxide TFT, a manufacturing method thereof, an array substrate and a display device. The Oxide TFT includes a base substrate; a gate electrode, a gate insulating layer and an active layer which are located on the base substrate; a source electrode and a drain electrode, the active layer is at least partly covered with the source electrode and the drain electrode; and a channel protection layer located between the source electrode and the drain electrode, each of the source electrode and the drain electrode includes at least part of a first metallic layer and at least part of a second metallic layer, the first metallic and the second metallic layer are stacked one on another, the channel protection layer is of a metal oxide.

3. 发明申请

US20190267406A1 THIN FILM TRANSISTOR, FABRICATION METHOD THEREFOR, AND ARRAY SUBSTRATE 审中-公开
公开(公告)号：US20190267406A1
公开(公告)日：2019-08-29
申请号：US16333032
申请日：2018-04-27
申请人： FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. , BOE TECHNOLOGY GROUP CO., LTD.
发明人： Xiaowei LIU , Bo LIU , Zhonghao HUANG , Chao FAN , Yang WANG , Yabin AN , Zheng LIU
IPC分类号： H01L27/12 , H01L29/786
摘要： The present disclosure provides a thin film transistor and a fabrication method thereof, and an array substrate. The thin film transistor formed on a base substrate, the thin film transistor includes: an active layer; a first signal metal layer, provided on a surface of the active layer facing the base substrate; a second signal metal layer, provided on a surface of the active layer facing away from the first signal metal layer, wherein, the active layer includes a conductive channel formation region, and the second signal metal layer does not cover the conductive channel formation region of the active layer.

4. 发明申请

US20150329432A1 Method for Preparing Polycrystalline Metal Oxide Pattern 有权
标题翻译：制备多晶金属氧化物图案的方法
公开(公告)号：US20150329432A1
公开(公告)日：2015-11-19
申请号：US14526777
申请日：2014-10-29
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Liangliang LI , Zongjie GUO , Huibin GUO , Shoukun WANG , Yuchun FENG , Xiaowei LIU
IPC分类号： C04B41/91 , C04B41/53 , C04B41/00
CPC分类号： H01L21/02691 , C04B41/0036 , C04B41/0072 , C04B41/5353 , C04B41/91 , H01L21/02422 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/02686
摘要： Disclosed is a method for preparing a polycrystalline metal oxide pattern, characterized by comprising: annealing a predetermined region of an amorphous metal oxide film by laser, so as to convert the amorphous metal oxide in the predetermined region into a polycrystalline metal oxide; and etching the amorphous metal oxide outside of the predetermined region so as to remove it. By the method according to the present invention, firstly, the predetermined region of an amorphous metal oxide film is annealed by laser so as to convert the amorphous metal oxide into a polycrystalline metal oxide, and then, the amorphous metal oxide outside of the predetermined region is etched away, thereby a polycrystalline metal oxide pattern is formed. The method for preparing a polycrystalline metal oxide pattern according to the present invention is simple, and can effectively shorten the production period and save production costs.
摘要翻译：公开了一种制备多晶金属氧化物图案的方法，其特征在于包括：通过激光对预定区域的非晶金属氧化物膜进行退火，以将预定区域中的非晶态金属氧化物转化成多晶金属氧化物; 并且在预定区域外蚀刻非晶态金属氧化物以便将其去除。根据本发明的方法，首先，通过激光对非晶金属氧化物膜的预定区域进行退火，以将非晶金属氧化物转化为多晶金属氧化物，然后在预定区域外部的非晶态金属氧化物被蚀刻掉，从而形成多晶金属氧化物图案。根据本发明的多晶金属氧化物图案的制备方法简单，可以有效缩短生产周期，节省生产成本。

5. 发明申请

US20150348999A1 Manufacturing Method of an Array Substrate 有权
标题翻译：阵列基板的制造方法
公开(公告)号：US20150348999A1
公开(公告)日：2015-12-03
申请号：US14519480
申请日：2014-10-21
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Huibin GUO , Shoukun WANG , Xiaowei LIU , Yuchun FENG , Zongjie GUO
IPC分类号： H01L27/12 , H01L29/45 , H01L29/49
CPC分类号： H01L27/1262 , H01L27/1288 , H01L29/458 , H01L29/4908
摘要： Provided is a manufacturing method of an array substrate with an etching stop layer. The method includes: forming a pattern including a gate, a gate line and a common electrode line on a substrate through a first patterning process; forming a gate insulation layer, an active layer film and an etching stop layer through a second patterning process; wherein, the etching stop layer corresponds to a gap between a source and a drain which are to be formed, and a via hole exposing the common electrode line is formed above the common electrode line; forming at least an active layer, a pattern including source, drain and data line and a protection layer through a third patterning process; wherein, the protection layer exposes a part of the drain; and forming at least a pixel electrode through a fourth patterning process; wherein, the pixel electrode is electrically connected with the drain.
摘要翻译：提供了具有蚀刻停止层的阵列基板的制造方法。该方法包括：通过第一图案化工艺在衬底上形成包括栅极，栅极线和公共电极线的图案; 通过第二图案化工艺形成栅极绝缘层，有源层膜和蚀刻停止层; 其中，所述蚀刻停止层对应于要形成的源极和漏极之间的间隙，并且在所述公共电极线上方形成暴露所述公共电极线的通孔; 通过第三图案化工艺形成至少有源层，包括源极，漏极和数据线的图案和保护层; 其中，所述保护层暴露所述漏极的一部分; 以及通过第四图案化工艺形成至少一个像素电极; 其中，像素电极与漏极电连接。

6. 发明申请

US20150318362A1 THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄膜晶体管及其制造方法，阵列基板及其制造方法
公开(公告)号：US20150318362A1
公开(公告)日：2015-11-05
申请号：US14406892
申请日：2014-06-18
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Shoukun WANG , Huibin GUO , Yuchun FENG , Xiaowei LIU , Zongjie GUO
IPC分类号： H01L29/417 , H01L27/12 , H01L29/66 , H01L29/786 , H01L21/283 , H01L21/027
CPC分类号： H01L29/41733 , H01L21/0273 , H01L21/283 , H01L27/1222 , H01L27/1288 , H01L29/66742 , H01L29/66765 , H01L29/786
摘要： A thin film transistor and manufacturing method thereof, an array substrate (1) comprising the thin film transistor and manufacturing method thereof. The method of manufacturing the thin film transistor comprises forming an active layer (4) and a source-drain electrode layer (5), forming a photoresist layer (6) on the source-drain electrode layer (5) and forming a pattern of the photoresist layer by a pattern process; etching the source-drain electrode layer (5) by using the pattern of the photoresist layer as a mask to form a pattern of the source-drain electrode layer including a source electrode and a drain electrode; and removing the photoresist, then etching the active layer (4) by using the pattern of the source-drain electrode layer as a mask to form a pattern of the active layer. The method of manufacturing the thin film transistor and the array substrate can prevent or decrease the possibility of the region of the active layer between the source electrode and the drain electrode in the thin film transistor being polluted by organics, thereby improve the electrical performance of the thin film transistor.
摘要翻译：一种薄膜晶体管及其制造方法，包括薄膜晶体管的阵列基板（1）及其制造方法。制造薄膜晶体管的方法包括形成有源层（4）和源极 - 漏极电极层（5），在源极 - 漏极电极层（5）上形成光刻胶层（6）并形成光刻胶层通过图案处理; 通过使用光致抗蚀剂层的图案作为掩模来蚀刻源极 - 漏极电极层（5），以形成包括源电极和漏电极的源极 - 漏极电极层的图案; 并去除光致抗蚀剂，然后通过使用源极 - 漏极电极层的图案作为掩模来蚀刻有源层（4）以形成有源层的图案。制造薄膜晶体管和阵列基板的方法可以防止或减少薄膜晶体管中的源电极和漏电极之间的有源层的区域被有机物污染的可能性，从而提高薄膜晶体管的电性能薄膜晶体管。

7. 发明申请

US20150311039A1 Dry Etching Method 有权
标题翻译：干法蚀刻法
公开(公告)号：US20150311039A1
公开(公告)日：2015-10-29
申请号：US14447915
申请日：2014-07-31
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Xiangqian DING , Yao LIU , Xi CHEN , Liangliang LI , Jinchao BAI , Xiaowei LIU
IPC分类号： H01J37/32
CPC分类号： H01J37/32082 , H01J37/3244 , H01J2237/334 , H01L21/31116
摘要： The present invention discloses a dry etching method. The dry etching method comprises: etching a first medium layer; introducing a second reaction gas in a reaction chamber, and exciting the second reaction gas into plasmas with a second radiofrequency power, so that the plasmas formed from the second reaction gas are combined with particulate pollutants in the reaction chamber, and in this case the reaction chamber is vacuumized to perform conversion processing; and etching a second medium layer. The technical solution of the present invention is capable of effectively preventing particulate pollutants from falling onto the glass substrate in the procedure of executing conversion processing, meanwhile, the effect of chamber purifying through vacuumizing is improved, and the amount of the particulate pollutants in the reaction chamber is effectively reduced.
摘要翻译：本发明公开了一种干式蚀刻方法。干蚀刻方法包括：蚀刻第一介质层; 在反应室中引入第二反应气体，并以第二射频功率将第二反应气体激发成等离子体，使得由第二反应气体形成的等离子体与反应室中的颗粒污染物组合，在这种情况下反应真空室进行转化处理; 并蚀刻第二介质层。本发明的技术方案在执行转化处理的过程中能够有效地防止颗粒污染物落入玻璃基板上，同时通过真空度提高室内净化的效果，反应中颗粒污染物的量室被有效地减少。

8. 发明申请

US20170285807A1 Touch Display Panel, Method For Fabrication Thereof And Display Device 审中-公开
公开(公告)号：US20170285807A1
公开(公告)日：2017-10-05
申请号：US15511497
申请日：2016-04-14
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Xiaowei LIU , Yao LIU , Liangliang LI , Xiangqian DING , Jinchao BAI
IPC分类号： G06F3/044 , G06F3/041
CPC分类号： G06F3/044 , G06F3/041 , G06F3/0412 , G06F2203/04103 , G06F2203/04107 , G06F2203/04111 , G06F2203/04112
摘要： The embodiments of the disclosure disclose a touch display panel, a method for fabrication thereof and a display device. The touch display panel comprises a display substrate, a transparent conductive layer formed on the display substrate, a transparent insulating layer formed on the transparent conductive layer, and a touch electrode formed on the transparent insulating layer. The embodiments of the disclosure can reduce accumulation of static electricity in the manufacture procedure of the display substrate and prevent electromagnetic interference when performing cell test by adding a transparent conductive layer and a transparent insulating layer between the touch substrate and the touch electrode.

9. 发明申请

US20150236128A1 THIN-FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, TFT ARRAY SUBSTRATE AND DISPLAY DEVICE 有权
标题翻译：薄膜晶体管及其制造方法，TFT阵列基板和显示装置
公开(公告)号：US20150236128A1
公开(公告)日：2015-08-20
申请号：US14466218
申请日：2014-08-22
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
发明人： Shoukun WANG , Huibin GUO , Xiaowei LIU , Yuchun FENG , Zongjie GUO
IPC分类号： H01L29/66 , H01L29/786 , H01L27/12 , H01L21/265
CPC分类号： H01L21/02694 , H01L21/02592 , H01L21/2253 , H01L21/265 , H01L21/26513 , H01L27/1214 , H01L27/127 , H01L29/66742 , H01L29/66765 , H01L29/786 , H01L29/78669 , H01L29/78696
摘要： The present invention discloses a method for manufacturing a thin-film transistor, comprising the steps of: forming a semiconductor active layer, and a doped semiconductor active layer; forming a source-drain metal layer; forming a channel region; and implanting ions for lowering the TFT leakage current into the surface of the semiconductor active layer in the channel region via ion implantation after forming the channel region. The invention further relates to a thin-film transistor, a TFT array substrate and a display device. The invention has the following beneficial effects: by implanting ions for lowering the TFT leakage current into the channel region, the electrical performance of a TFT may be improved, and the thickness of a semiconductor active layer in a channel region may be changed controllably.
摘要翻译：本发明公开了一种制造薄膜晶体管的方法，包括以下步骤：形成半导体有源层和掺杂的半导体有源层; 形成源极 - 漏极金属层; 形成通道区域; 以及在形成沟道区域之后通过离子注入注入用于将TFT漏电流降低到沟道区中的半导体有源层的表面中的离子。本发明还涉及薄膜晶体管，TFT阵列基板和显示装置。本发明具有以下有益效果：通过注入用于将TFT漏电流降低到沟道区域中的离子，可以提高TFT的电性能，并且可以可控地改变沟道区中半导体活性层的厚度。

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