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1. 发明申请

US20090204767A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERALIZED LRU IN CACHE AND MEMORY PERFORMANCE ANALYSIS AND MODELING 失效
标题翻译：方法，系统和计算机程序产品在缓存中的通用LRU和内存性能分析与建模
公开(公告)号：US20090204767A1
公开(公告)日：2009-08-13
申请号：US12030501
申请日：2008-02-13
申请人： David S. Hutton , Keith N. Langston , Kathryn M. Jackson , Hanno Ulrich , Craig R. Walters
发明人： David S. Hutton , Keith N. Langston , Kathryn M. Jackson , Hanno Ulrich , Craig R. Walters
IPC分类号： G06F12/08
CPC分类号： G06F12/122 , G06F12/0864
摘要： The exemplary embodiment of the present invention relates to a generalized LRU algorithm is provided that is associated with a specified cache associativity line set value that is determined by a system user. As configured, the LRU algorithm as presented can comprise n-levels for an LRU tree, each specified tree being individually analyzed within the LRU algorithm. Within each LRU tree level comprises the associativity line value can be further broken down into sub-analysis groups of any desired configuration, however, the total sub-analysis group configuration must equal the specified cache associativity line value.
摘要翻译：本发明的示例性实施例涉及与由系统用户确定的指定的高速缓存关联性线路集值相关联的广义LRU算法。如所配置的，所呈现的LRU算法可以包括用于LRU树的n级，每个指定的树在LRU算法内单独分析。在每个LRU树级包括相关性线值可以进一步分解成任何所需配置的子分析组，然而，总子分析组配置必须等于指定的高速缓存关联性线值。

2. 发明授权

US08566529B2 Method, system and computer program product for generalized LRU in cache and memory performance analysis and modeling 失效
标题翻译：用于广义LRU的方法，系统和计算机程序产品在缓存和存储器性能分析和建模中的应用
公开(公告)号：US08566529B2
公开(公告)日：2013-10-22
申请号：US12030501
申请日：2008-02-13
申请人： David S. Hutton , Keith N. Langston , Kathryn M. Jackson , Hanno Ulrich , Craig R. Walters
发明人： David S. Hutton , Keith N. Langston , Kathryn M. Jackson , Hanno Ulrich , Craig R. Walters
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/44 , G06F13/10 , G06F13/12
CPC分类号： G06F12/122 , G06F12/0864
摘要： The exemplary embodiment of the present invention relates to a generalized LRU algorithm is provided that is associated with a specified cache associativity line set value that is determined by a system user. As configured, the LRU algorithm as presented can comprise n-levels for an LRU tree, each specified tree being individually analyzed within the LRU algorithm. Within each LRU tree level comprises the associativity line value can be further broken down into sub-analysis groups of any desired configuration, however, the total sub-analysis group configuration must equal the specified cache associativity line value.
摘要翻译：本发明的示例性实施例涉及与由系统用户确定的指定的高速缓存关联性线路集值相关联的广义LRU算法。如所配置的，所呈现的LRU算法可以包括用于LRU树的n级，每个指定的树在LRU算法内单独分析。在每个LRU树级包括相关性线值可以进一步分解成任何所需配置的子分析组，然而，总子分析组配置必须等于指定的高速缓存关联性线值。

3. 发明申请

US20110320743A1 MEMORY ORDERED STORE SYSTEM IN A MULTIPROCESSOR COMPUTER SYSTEM 有权
标题翻译：多处理器计算机系统中的存储订单存储系统
公开(公告)号：US20110320743A1
公开(公告)日：2011-12-29
申请号：US12822331
申请日：2010-06-24
申请人： Norbert Hagspiel , Matthias Klein , Ulrich Mayer , Robert J. Sonnelitter, III , Gary E. Strait , Hanno Ulrich
发明人： Norbert Hagspiel , Matthias Klein , Ulrich Mayer , Robert J. Sonnelitter, III , Gary E. Strait , Hanno Ulrich
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F9/3842 , G06F9/528 , G06F12/0828 , G06F12/0831 , G06F12/0862 , G06F12/1054 , G06F2212/1016 , G06F2212/507 , G06F2212/621
摘要： A system and computer implemented method for storing of data in the memory of a computer system in order at a fast rate is provided. The method includes launching a first store to memory. A wait counter is initiated. A second store to memory is speculatively launched when the wait counter expires. The second store to memory is cancelled when the second store achieves coherency prior to the first store to memory.
摘要翻译：提供了一种用于以快速的顺序将数据存储在计算机系统的存储器中的系统和计算机实现的方法。该方法包括向存储器启动第一个存储。启动等待计数器。当等待计数器到期时，第二家存储器被推测启动。当第二个存储在第一个存储到存储器之前实现相关性时，第二个存储器的存储被取消。

4. 发明授权

US08850129B2 Memory ordered store system in a multiprocessor computer system 有权
标题翻译：内存订购存储系统在多处理器计算机系统中
公开(公告)号：US08850129B2
公开(公告)日：2014-09-30
申请号：US12822331
申请日：2010-06-24
申请人： Norbert Hagspiel , Matthias Klein , Ulrich Mayer , Robert J. Sonnelitter, III , Gary E. Strait , Hanno Ulrich
发明人： Norbert Hagspiel , Matthias Klein , Ulrich Mayer , Robert J. Sonnelitter, III , Gary E. Strait , Hanno Ulrich
IPC分类号： G06F12/02 , G06F12/08 , G06F9/38 , G06F12/10 , G06F9/52
CPC分类号： G06F12/0815 , G06F9/3842 , G06F9/528 , G06F12/0828 , G06F12/0831 , G06F12/0862 , G06F12/1054 , G06F2212/1016 , G06F2212/507 , G06F2212/621
摘要： A system and computer implemented method for storing of data in the memory of a computer system in order at a fast rate is provided. The method includes launching a first store to memory. A wait counter is initiated. A second store to memory is speculatively launched when the wait counter expires. The second store to memory is cancelled when the second store achieves coherency prior to the first store to memory.
摘要翻译：提供了一种用于以快速的顺序将数据存储在计算机系统的存储器中的系统和计算机实现的方法。该方法包括向存储器启动第一个存储。启动等待计数器。当等待计数器到期时，第二家存储器被推测启动。当第二个存储在第一个存储到存储器之前实现相关性时，第二个存储器的存储被取消。

5. 发明申请

US20090217269A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING MULTIPLE QUIESCE STATE MACHINES 有权
标题翻译：用于提供多种状态机器的系统，方法和计算机程序产品
公开(公告)号：US20090217269A1
公开(公告)日：2009-08-27
申请号：US12037734
申请日：2008-02-26
申请人： Lisa C. Heller , Norbert Hagspiel , Ute Gaertner , Hanno Ulrich , Rebecca S. Wisniewski
发明人： Lisa C. Heller , Norbert Hagspiel , Ute Gaertner , Hanno Ulrich , Rebecca S. Wisniewski
IPC分类号： G06F9/46
CPC分类号： G06F12/1027 , G06F9/52 , G06F12/10 , G06F2212/682 , G06F2212/683
摘要： A system, method and computer program product for providing multiple quiesce state machines. The system includes a first controller including logic for processing a first quiesce request. The system also includes a second controller including logic for processing a second quiesce request. All or a portion of the processing of the second quiesce request overlaps in time with the processing of the first quiesce request. Thus, multiple quiesce requests may be active in the system at the same time.
摘要翻译：一种用于提供多个静默状态机的系统，方法和计算机程序产品。该系统包括第一控制器，其包括用于处理第一静默请求的逻辑。该系统还包括第二控制器，其包括用于处理第二静默请求的逻辑。处理第二停顿请求的全部或一部分与处理第一停顿请求的时间重叠。因此，多个静默请求可能在系统中同时处于活动状态。

6. 发明授权

US08572624B2 Providing multiple quiesce state machines in a computing environment 有权
标题翻译：在计算环境中提供多个静默状态机
公开(公告)号：US08572624B2
公开(公告)日：2013-10-29
申请号：US12037734
申请日：2008-02-26
申请人： Lisa C. Heller , Norbert Hagspiel , Ute Gaertner , Hanno Ulrich , Rebecca S. Wisniewski
发明人： Lisa C. Heller , Norbert Hagspiel , Ute Gaertner , Hanno Ulrich , Rebecca S. Wisniewski
IPC分类号： G06F9/46 , G06F7/38
CPC分类号： G06F12/1027 , G06F9/52 , G06F12/10 , G06F2212/682 , G06F2212/683
摘要： A system, method and computer program product for providing multiple quiesce state machines. The system includes a first controller including logic for processing a first quiesce request. The system also includes a second controller including logic for processing a second quiesce request. All or a portion of the processing of the second quiesce request overlaps in time with the processing of the first quiesce request. Thus, multiple quiesce requests may be active in the system at the same time.
摘要翻译：一种用于提供多个静默状态机的系统，方法和计算机程序产品。该系统包括第一控制器，其包括用于处理第一静默请求的逻辑。该系统还包括第二控制器，其包括用于处理第二静默请求的逻辑。处理第二停顿请求的全部或一部分与处理第一停顿请求的时间重叠。因此，多个静默请求可能在系统中同时处于活动状态。

7. 发明授权

US08090883B2 Method, system and computer program product for enhanced shared store buffer management scheme with limited resources for optimized performance 有权
标题翻译：方法，系统和计算机程序产品，用于增强共享存储缓冲区管理方案，有限的资源用于优化性能
公开(公告)号：US08090883B2
公开(公告)日：2012-01-03
申请号：US12850198
申请日：2010-08-04
申请人： Gary E. Strait , Mark A. Check , Hong Deng , Diana L. Orf , Hanno Ulrich
发明人： Gary E. Strait , Mark A. Check , Hong Deng , Diana L. Orf , Hanno Ulrich
IPC分类号： G06F13/00
CPC分类号： G06F13/4059
摘要： The exemplary embodiment of the present invention provides a storage buffer management scheme for I/O store buffers. Specifically, the storage buffer management system as described within the exemplary embodiment of the present invention is configured to comprise storage buffers that have the capability to efficiently support 128 byte or 256 byte I/O data transmission lines. The presently implemented storage buffer management scheme enables for a limited number of store buffers to be associated with a fixed number of storage state machines (i.e., queue positions) and thereafter the allowing for the matched pairs to be allocated in order to achieve maximum store throughput for varying combinations of store sizes of 128 and 256 bytes.
摘要翻译：本发明的示例性实施例提供了用于I / O存储缓冲器的存储缓冲器管理方案。具体地说，在本发明的示例性实施例中描述的存储缓冲器管理系统被配置为包括具有有效支持128字节或256字节的I / O数据传输线的能力的存储缓冲器。目前实现的存储缓冲器管理方案使得有限数量的存储缓冲器能够与固定数量的存储状态机（即，队列位置）相关联，并且之后允许分配匹配的对以便实现最大存储吞吐量适用于128和256字节存储大小的不同组合。

8. 发明授权

US07174426B2 Interleave pre-checking in front of shared caches with pipelined access 失效
标题翻译：在流水线访问共享缓存之前交叉预检
公开(公告)号：US07174426B2
公开(公告)日：2007-02-06
申请号：US10896500
申请日：2004-07-22
申请人： Hanno Ulrich
发明人： Hanno Ulrich
IPC分类号： G06F12/08
CPC分类号： G06F9/3824 , G06F12/0851
摘要： The invention relates to a method and respective system for accessing a cache memory in a computer system, wherein the cache memory is split up in at least two segments, wherein the cache memory is accessed by a plurality of competing cache memory requests via a number of commonly used input registers, wherein a cache segment model is utilized for reflecting the cache use by said competing requests, wherein cache memory requests are processed by a processing pipe and wherein each cache-request, before entering the processing pipe, is checked whether the segments of the cache memory are available at the cycle it needs, wherein said memory comprises the steps of: a) marking a segment model cell as busy with storing, if a store-request targeting to a cache segment corresponding to said model cell has received pipe access, b) blocking off from pipe access a fetch-request targeting to a segment model cell, which is marked busy with a store operation; and c) blocking off any store-request from pipe access, if at least one fetch request, which was blocked off from pipe access according to step b), is waiting for pipe access.
摘要翻译：本发明涉及一种用于访问计算机系统中的高速缓冲存储器的方法和相应的系统，其中高速缓冲存储器被分成至少两个段，其中高速缓冲存储器被多个竞争的高速缓冲存储器请求经由多个常用的输入寄存器，其中高速缓存段模型用于通过所述竞争请求来反映高速缓存使用，其中高速缓存存储器请求由处理管线处理，并且其中在进入处理管道之前检查每个高速缓存请求是否是段所述存储器包括以下步骤：a）将段模型单元标记为忙于存储，如果针对对应于所述模型单元的高速缓存段的存储请求已经接收到管道访问，b）阻止管道访问针对被标记为忙于存储操作的段模型单元的提取请求定向; 以及c）如果根据步骤b）从管道访问被阻止的至少一个提取请求等待管道访问，则阻止任何存储请求从管道访问。

9. 发明申请

US20050027942A1 Interleave pre-checking in front of shared caches with pipelined access 失效
标题翻译：在流水线访问共享缓存之前交叉预检
公开(公告)号：US20050027942A1
公开(公告)日：2005-02-03
申请号：US10896500
申请日：2004-07-22
申请人： Hanno Ulrich
发明人： Hanno Ulrich
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/3824 , G06F12/0851
摘要： The invention relates to a method and respective system for accessing a cache memory in a computer system, wherein the cache memory is split up in at least two segments, wherein the cache memory is accessed by a plurality of competing cache memory requests via a number of commonly used input registers, wherein a cache segment model is utilized for reflecting the cache use by said competing requests, wherein cache memory requests are processed by a processing pipe and wherein each cache-request, before entering the processing pipe, is checked whether the segments of the cache memory are available at the cycle it needs, wherein said memory comprises the steps of: a) marking a segment model cell as busy with storing, if a store-request targeting to a cache segment corresponding to said model cell has received pipe access, b) blocking off from pipe access a fetch-request targeting to a segment model cell, which is marked busy with a store operation; and c) blocking off any store-request from pipe access, if at least one fetch request, which was blocked off from pipe access according to step b), is waiting for pipe access.
摘要翻译：本发明涉及一种用于访问计算机系统中的高速缓冲存储器的方法和相应的系统，其中高速缓冲存储器被分成至少两个段，其中高速缓冲存储器被多个竞争的高速缓冲存储器请求经由多个常用的输入寄存器，其中高速缓存段模型用于通过所述竞争请求来反映高速缓存使用，其中高速缓存存储器请求由处理管线处理，并且其中在进入处理管道之前检查每个高速缓存请求是否是段所述存储器包括以下步骤：a）将段模型单元标记为忙于存储，如果针对对应于所述模型单元的高速缓存段的存储请求已经接收到管道访问，b）阻止管道访问针对被标记为忙于存储操作的段模型单元的提取请求定向; 以及c）如果根据步骤b）从管道访问被阻止的至少一个提取请求等待管道访问，则阻止任何存储请求从管道访问。

10. 发明申请

US20100325321A1 Method, System and Computer Program Product for Enhanced Shared Store Buffer Management Scheme with Limited Resources for Optimized Performance 有权
标题翻译：方法，系统和计算机程序产品，用于增强共享存储缓冲区管理方案，有限资源用于优化性能
公开(公告)号：US20100325321A1
公开(公告)日：2010-12-23
申请号：US12850198
申请日：2010-08-04
申请人： Gary E. Strait , Mark A. Check , Hong Deng , Diana L. Orf , Hanno Ulrich
发明人： Gary E. Strait , Mark A. Check , Hong Deng , Diana L. Orf , Hanno Ulrich
IPC分类号： G06F5/00
CPC分类号： G06F13/4059
摘要： The exemplary embodiment of the present invention provides a storage buffer management scheme for I/O store buffers. Specifically, the storage buffer management system as described within the exemplary embodiment of the present invention is configured to comprise storage buffers that have the capability to efficiently support 128 byte or 256 byte I/O data transmission lines. The presently implemented storage buffer management scheme enables for a limited number of store buffers to be associated with a fixed number of storage state machines (i.e., queue positions) and thereafter the allowing for the matched pairs to be allocated in order to achieve maximum store throughput for varying combinations of store sizes of 128 and 256 bytes.
摘要翻译：本发明的示例性实施例提供了用于I / O存储缓冲器的存储缓冲器管理方案。具体地说，在本发明的示例性实施例中描述的存储缓冲器管理系统被配置为包括具有有效支持128字节或256字节的I / O数据传输线的能力的存储缓冲器。目前实现的存储缓冲器管理方案使得有限数量的存储缓冲器能够与固定数量的存储状态机（即，队列位置）相关联，并且之后允许分配匹配的对以便实现最大存储吞吐量适用于128和256字节存储大小的不同组合。

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