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1. 发明授权

US08767444B2 Radiation-hardened memory element with multiple delay elements 有权
标题翻译：具有多个延迟元件的辐射硬化存储元件
公开(公告)号：US08767444B2
公开(公告)日：2014-07-01
申请号：US11389767
申请日：2006-03-27
申请人： David Nelson , Keith Golke , Harry H L Liu , Michael Liu
发明人： David Nelson , Keith Golke , Harry H L Liu , Michael Liu
IPC分类号： G11C11/41 , G11C11/412 , G11C11/413 , G11C11/417 , G11C7/02 , G11C7/24 , G11C5/02 , G11C5/06
CPC分类号： G11C11/4125 , G11C5/005
摘要： A radiation hardened memory element includes at least two delay elements for maintaining radiation hardness. In an example, the memory element is an SRAM cell. Both delays are coupled together in series so that if either one of the delays fails, a delay will still be maintained within the SRAM cell. The critical areas of the delays may be positioned so that a common line of sight cannot be made between each delay and a circuit node.
摘要翻译：辐射硬化的存储元件包括用于保持辐射硬度的至少两个延迟元件。在一个示例中，存储器元件是SRAM单元。两个延迟都串联在一起，使得如果任一个延迟失败，则在SRAM单元内仍将保持延迟。延迟的关键区域可以定位成使得在每个延迟和电路节点之间不能产生共同的视线。

2. 发明申请

US20070242537A1 Radiation-hardened memory element with multiple delay elements 有权
标题翻译：具有多个延迟元件的辐射硬化存储元件
公开(公告)号：US20070242537A1
公开(公告)日：2007-10-18
申请号：US11389767
申请日：2006-03-27
申请人： Keith Golke , Harry Liu , Michael Liu , David Nelson
发明人： Keith Golke , Harry Liu , Michael Liu , David Nelson
IPC分类号： G11C7/00
CPC分类号： G11C11/4125 , G11C5/005
摘要： A radiation hardened memory element includes at least two delay elements for maintaining radiation hardness. In an example, the memory element is an SRAM cell. Both delays are coupled together in series so that if either one of the delays fails, a delay will still be maintained within the SRAM cell. The critical areas of the delays may be positioned so that a common line of sight cannot be made between each delay and a circuit node.
摘要翻译：辐射硬化的存储元件包括用于保持辐射硬度的至少两个延迟元件。在一个示例中，存储器元件是SRAM单元。两个延迟都串联在一起，使得如果任一个延迟失败，则在SRAM单元内仍将保持延迟。延迟的关键区域可以定位成使得在每个延迟和电路节点之间不能产生共同的视线。

3. 发明申请

US20070279964A1 SRAM split write control for a delay element 审中-公开
标题翻译：用于延迟元件的SRAM分离写入控制
公开(公告)号：US20070279964A1
公开(公告)日：2007-12-06
申请号：US11440892
申请日：2006-05-25
申请人： Keith Golke , Harry Liu , David Nelson
发明人： Keith Golke , Harry Liu , David Nelson
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/02 , G11C5/005 , G11C8/14 , G11C11/4125
摘要： A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.
摘要翻译：描述具有分离写入控制的静态随机存取存储器（SRAM）。 SRAM包括位，写和写字线。 SRAM内的每个存储单元包括耦合到专用写字线的延迟。当单元未被写入时，其延迟在其相关联的写字线上接收延迟信号，这增加了单元的响应时间。然而，当单元被写入时，其延迟在其相关的写字线上接收旁路信号，这降低了SRAM单元的响应时间。

4. 发明申请

US20070096754A1 Method and system for analyzing single event upset in semiconductor devices 审中-公开
标题翻译：用于分析半导体器件中的单事件不正常的方法和系统
公开(公告)号：US20070096754A1
公开(公告)日：2007-05-03
申请号：US11265824
申请日：2005-11-03
申请人： Michael Johnson , Keith Golke , Pamela Vogt , David Nelson
发明人： Michael Johnson , Keith Golke , Pamela Vogt , David Nelson
IPC分类号： G01R31/302
CPC分类号： G01R31/3181 , G01R31/31816
摘要： A simulation model is used to predict a semiconductor device's response to a single event upset. The simulation model is connected to a model of the semiconductor device to be tested. The simulation model switches in an impedance path between a node to be tested in the semiconductor device model and an opposite voltage supply until a predefined amount of charge has been reached via sourcing (for a low to high voltage transition) or sinking (for a high to low voltage transition). When the predefined amount of charge has been reached, the impedance path is switched out. The switching of the impedance path approximates the charge movement that occurs from a heavy ion strike passing through a sensitive volume. By varying the predefined amount of charge, the semiconductor device's susceptibility to SEU can be predicted without having to resort to physical testing.
摘要翻译：模拟模型用于预测半导体器件对单个事件不安的响应。仿真模型连接到要测试的半导体器件的模型。模拟模型切换半导体器件模型中要测试的节点之间的阻抗路径和相反的电源，直到通过源（达到低电压转换）或下沉（达到高电平）达到预定量的电荷到低压转换）。当达到预定量的电荷时，阻抗路径被切断。阻抗路径的切换近似于通过敏感体积的重离子冲击发生的电荷运动。通过改变预定量的电荷，可以预测半导体器件对SEU的敏感性，而无需诉诸于物理测试。

5. 发明申请

US20080106955A1 SRAM Split Write Control for a Delay Element 有权
标题翻译： SRAM分离写延迟元件的写控制
公开(公告)号：US20080106955A1
公开(公告)日：2008-05-08
申请号：US12013856
申请日：2008-01-14
申请人： Keith Golke , Harry Liu , David Nelson
发明人： Keith Golke , Harry Liu , David Nelson
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C5/005 , G11C8/14 , G11C11/4125
摘要： A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.
摘要翻译：描述具有分离写入控制的静态随机存取存储器（SRAM）。 SRAM包括位，写和写字线。 SRAM内的每个存储单元包括耦合到专用写字线的延迟。当单元未被写入时，其延迟在其相关联的写字线上接收延迟信号，这增加了单元的响应时间。然而，当单元被写入时，其延迟在其相关的写字线上接收旁路信号，这降低了SRAM单元的响应时间。

6. 发明申请

US20060145086A1 Dose rate simulation 有权
标题翻译：剂量率模拟
公开(公告)号：US20060145086A1
公开(公告)日：2006-07-06
申请号：US11029308
申请日：2005-01-05
申请人： Harry Liu , Keith Golke , Eric Vogt , Michael Liu
发明人： Harry Liu , Keith Golke , Eric Vogt , Michael Liu
IPC分类号： G01T1/24
CPC分类号： G06F17/5036
摘要： Behaviors of a transistor during a dose rate event can be modeled using a circuit simulation software package. A subcircuit model replaces a transistor in a circuit design to be simulated. The subcircuit model can be in the form of a schematic-based representation or a netlist. The subcircuit model provides a model of a source junction and a drain junction in the transistor during the dose rate event. The subcircuit model also includes the size of the transistor being replaced and the dose rate of the dose rate event. Once the transistor is replaced with the subcircuit model, a dose rate simulation may be performed to determine the dose rate hardness of the circuit design.
摘要翻译：在剂量率事件期间晶体管的行为可以使用电路仿真软件包进行建模。子电路模型取代要仿真的电路设计中的晶体管。子电路模型可以是基于原理图的表示形式或网表。子电路模型在剂量率事件期间提供晶体管中的源极结和漏极结的模型。子电路模型还包括被替换的晶体管的尺寸和剂量率事件的剂量率。一旦晶体管被子电路模型替代，可以执行剂量率模拟来确定电路设计的剂量率硬度。

7. 发明授权

US08570061B2 (N-1)-out-of-N voter mux with enhanced drive 有权
标题翻译：（N-1）-out-of-N选民复合机，具有增强的驱动力
公开(公告)号：US08570061B2
公开(公告)日：2013-10-29
申请号：US13176405
申请日：2011-07-05
申请人： Keith Golke
发明人： Keith Golke
IPC分类号： H03K19/003
CPC分类号： H03K19/00338
摘要： This disclosure describes voting circuits where an output is generated based on a plurality of inputs. A first plurality of logic paths connects the output to a high voltage. Each logic path of the first plurality of logic paths includes two transistors. A second plurality of logic paths connects the output to the low voltage. Each logic path of the second plurality of logic paths comprises two transistors. Based on N or N−1 of the inputs agreeing, the output is driven to either the low voltage or the high voltage via a subset of logic paths of the first and second plurality of logic paths.
摘要翻译：本公开描述了基于多个输入产生输出的投票电路。第一多个逻辑路径将输出连接到高电压。第一多个逻辑路径的每个逻辑路径包括两个晶体管。第二多个逻辑路径将输出连接到低电压。第二多个逻辑路径的每个逻辑路径包括两个晶体管。基于输入的N或N-1同意，经由第一和第二多个逻辑路径的逻辑路径的子集将输出驱动为低电压或高电压。

8. 发明申请

US20110141636A1 NON-ALIGNED ANTENNA EFFECT PROTECTION CIRCUIT WITH SINGLE EVENT TRANSIENT HARDNESS 有权
标题翻译：非对准天线效果保护电路，具有单次瞬态硬度
公开(公告)号：US20110141636A1
公开(公告)日：2011-06-16
申请号：US12636314
申请日：2009-12-11
申请人： Keith Golke , Jeff Graebel
发明人： Keith Golke , Jeff Graebel
IPC分类号： H02H9/00
CPC分类号： H01L27/0255 , H01L27/0296 , H01L2924/0002 , H01L2924/00
摘要： The disclosure describes an antenna protection circuit for use in circuits where Single Event Transients from energetic particles is a concern. The antenna protection circuit may include at least three diodes, connected electrically in series and arranged such that at most all but one of the at least three diodes produce a transient current pulse from an energetic particle. During the transient current pulse event, the remaining diode remains reverse biased thereby sufficiently blocking the transient current pulse and an SET does not occur on the signal node. The antenna protection circuit may be constructed so that no unshorted parasitic p-n junction structure is associated with any of the diodes in the circuit, which would otherwise have to be explicitly included in the at least three diodes.
摘要翻译：本公开描述了一种用于电路中的天线保护电路，其中关注高能粒子的单事件瞬变。天线保护电路可以包括至少三个二极管，其串联电连接并且布置成使得至少三个二极管中的至少所有的二极管中的至少一个产生来自能量粒子的瞬态电流脉冲。在瞬态电流脉冲事件期间，剩余的二极管保持反向偏置，从而充分阻止瞬态电流脉冲，并且在信号节点上不发生SET。天线保护电路可以被构造成使得没有未排序的寄生p-n结结构与电路中的任何二极管相关联，否则这些二极管否则必须明确地包括在至少三个二极管中。

9. 发明申请

US20070063758A1 Voltage divider and method for minimizing higher than rated voltages 审中-公开
标题翻译：用于最小化额定电压的分压器和方法
公开(公告)号：US20070063758A1
公开(公告)日：2007-03-22
申请号：US11232734
申请日：2005-09-22
申请人： Thaddeus Allard , Keith Golke , Michael Johnson , Karu Vignarajah
发明人： Thaddeus Allard , Keith Golke , Michael Johnson , Karu Vignarajah
IPC分类号： H03L5/00
CPC分类号： H03K19/00315 , H03K17/102 , H03K17/6872
摘要： A voltage divider circuit can be realized by dividing a higher than rated operating voltage across a plurality of MOS transistors. The voltage divider circuit can be used for a wide variety of ratios of low and high operating voltages. Only one gate input voltage is needed, minimizing power dissipation, heat, and hot carrier effects. The voltage divider circuit is employed in a voltage driver circuit to generate a high output voltage in response to a low voltage input while minimizing damage to the MOS transistors within the voltage driver circuit.
摘要翻译：可以通过在多个MOS晶体管之间划分高于额定工作电压来实现分压器电路。分压器电路可用于各种各样的低和高工作电压比。只需要一个栅极输入电压，最大限度地减少功耗，热量和热载流子效应。分压器电路用于电压驱动器电路中，以响应于低电压输入而产生高输出电压，同时最小化电压驱动器电路内的MOS晶体管的损坏。

10. 发明申请

US20130027137A1 RADIATION HARDENED DIFFERENTIAL AMPLIFIER 有权
标题翻译：辐射硬化差分放大器
公开(公告)号：US20130027137A1
公开(公告)日：2013-01-31
申请号：US13190285
申请日：2011-07-25
申请人： James D. Seefeldt , Keith Golke
发明人： James D. Seefeldt , Keith Golke
IPC分类号： H03F3/68
CPC分类号： H03F3/45183 , H03F3/211 , H03F2203/45352 , H03F2203/45366 , H03F2203/45674
摘要： This disclosure is directed to techniques for preventing or reducing perturbations of an output signal of a differential amplifier caused by ionizing radiation incident upon the amplifier. The amplifier may include an amplification module that includes a plurality of amplification units configured to amplify a difference between a first component and a second component of a differential voltage signal to generate a plurality of amplified difference signals each corresponding to the amplified difference. The amplifier may further include a combination module that combines the plurality of amplified difference signals to generate a common output signal corresponding to the amplified difference.
摘要翻译：本公开涉及用于防止或减少由入射在放大器上的电离辐射引起的差分放大器的输出信号的扰动的技术。放大器可以包括放大模块，其包括多个放大单元，其被配置为放大差分电压信号的第一分量和第二分量之间的差，以产生每个对应于放大差值的多个放大差分信号。放大器还可以包括组合多个放大的差分信号以产生对应于放大差分的公共输出信号的组合模块。

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