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1. 发明授权

US08539130B2 Virtual channels for effective packet transfer 有权
标题翻译：用于有效数据包传输的虚拟通道
公开(公告)号：US08539130B2
公开(公告)日：2013-09-17
申请号：US12873057
申请日：2010-08-31
申请人： David B. Glasco , Dane T. Mrazek , Samuel H. Duncan , Patrick R. Marchand , Ravi Kiran Manyam , Yin Fung Tang , John H. Edmondson
发明人： David B. Glasco , Dane T. Mrazek , Samuel H. Duncan , Patrick R. Marchand , Ravi Kiran Manyam , Yin Fung Tang , John H. Edmondson
IPC分类号： G06F12/00 , G06F11/00
CPC分类号： G06F13/1605
摘要： The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting a data request or a data packet to a destination client subsystem based on the type of the source client subsystem and/or the type of data request. Higher priority traffic is transmitted over virtual channels that are configured to transmit data without causing deadlocks and/or stalls. Lower priority traffic is transmitted over virtual channels that can be stalled.
摘要翻译：本发明提出了一种包括多个虚拟通道的交叉开关单元，每个虚拟通道是横杠单元内的逻辑数据流。耦合到源客户端子系统的仲裁逻辑被配置为基于源客户端子系统的类型和/或数据请求的类型来选择用于将数据请求或数据分组发送到目的地客户端子系统的虚拟信道。较高优先级的流量通过配置为传输数据而不引起死锁和/或停顿的虚拟通道进行传输。较低优先级的流量可以通过虚拟通道进行传输，可以停滞。

2. 发明申请

US20110072177A1 VIRTUAL CHANNELS FOR EFFECTIVE PACKET TRANSFER 有权
标题翻译：用于有效分组传输的虚拟通道
公开(公告)号：US20110072177A1
公开(公告)日：2011-03-24
申请号：US12873057
申请日：2010-08-31
申请人： David B. Glasco , Dane T. Mrazek , Samuel H. Duncan , Patrick R. Marchand , Ravi Kiran Manyam , Yin Fung Tang , John H. Edmondson
发明人： David B. Glasco , Dane T. Mrazek , Samuel H. Duncan , Patrick R. Marchand , Ravi Kiran Manyam , Yin Fung Tang , John H. Edmondson
IPC分类号： G06F13/14 , G06F13/00
CPC分类号： G06F13/1605
摘要： The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting a data request or a data packet to a destination client subsystem based on the type of the source client subsystem and/or the type of data request. Higher priority traffic is transmitted over virtual channels that are configured to transmit data without causing deadlocks and/or stalls. Lower priority traffic is transmitted over virtual channels that can be stalled.
摘要翻译：本发明提出了一种包括多个虚拟通道的交叉开关单元，每个虚拟通道是横杠单元内的逻辑数据流。耦合到源客户端子系统的仲裁逻辑被配置为基于源客户端子系统的类型和/或数据请求的类型来选择用于将数据请求或数据分组发送到目的地客户端子系统的虚拟信道。较高优先级的流量通过配置为传输数据而不引起死锁和/或停顿的虚拟通道进行传输。较低优先级的流量可以通过虚拟通道进行传输，可以停滞。

3. 发明授权

US09098383B1 Consolidated crossbar that supports a multitude of traffic types 有权
标题翻译：合并的交叉开关，支持多种流量类型
公开(公告)号：US09098383B1
公开(公告)日：2015-08-04
申请号：US12792684
申请日：2010-06-02
申请人： Sean J. Treichler , Dane T. Mrazek , Yin Fung (David) Tang , David B. Glasco , Colyn Scott Case , Emmett M. Kilgariff
发明人： Sean J. Treichler , Dane T. Mrazek , Yin Fung (David) Tang , David B. Glasco , Colyn Scott Case , Emmett M. Kilgariff
IPC分类号： G06F13/00 , H04J3/14 , G06F5/00 , H04L12/26 , H04J3/16 , H04J3/22 , H04L12/54
CPC分类号： G06F13/00 , G06F5/00 , H04J3/14 , H04J3/16 , H04J3/22 , H04L12/54 , H04L12/6418 , H04L47/521 , H04L47/522
摘要： One embodiment of the present invention sets forth a crossbar unit that is coupled to a plurality of client subsystems. The crossbar unit is configured to transmit data packets between the client subsystems and includes a high-bandwidth channel and a narrow-bandwidth channel. The high-bandwidth channel is used for transmitting large data packets, while the narrow-bandwidth is used for transmitting smaller data packets. The transmission of data packets may be prioritized based on the source and destination clients as well as the type of data being transmitted. Further, the crossbar unit includes a buffer mechanism for buffering data packets received from source clients until those data packets can be received by the destination clients.
摘要翻译：本发明的一个实施例提出了一种连接到多个客户端子系统的交叉开关单元。交叉开关单元被配置为在客户端子系统之间传输数据分组，并且包括高带宽信道和窄带宽信道。高带宽信道用于传输大数据包，而窄带用于传输较小的数据包。可以基于源和目的地客户端以及正在发送的数据的类型来优先考虑数据分组的传输。此外，交叉开关单元包括用于缓冲从源客户端接收到的数据分组的缓冲机构，直到目的地客户端可以接收到这些数据分组。

4. 发明授权

US06778181B1 Graphics processing system having a virtual texturing array 有权
标题翻译：具有虚拟纹理阵列的图形处理系统
公开(公告)号：US06778181B1
公开(公告)日：2004-08-17
申请号：US10012895
申请日：2001-12-07
申请人： Emmett M. Kilgariff , Dane T. Mrazek
发明人： Emmett M. Kilgariff , Dane T. Mrazek
IPC分类号： G09G500
CPC分类号： G06T15/503 , G06T15/005 , G06T15/04
摘要： A graphics processing system is provided. The graphics processing system includes a front end module for receiving pixel data. A setup unit is coupled to the front end module and generates parameter coefficients. A raster unit is coupled to the setup unit and generates stepping information. A virtual texturing array engine textures and colors the pixel data based on the parameter coefficients and stepping information. Also provided is a pixel engine adapted for processing the textured and colored pixel data received from the virtual texturing array engine.
摘要翻译：提供图形处理系统。图形处理系统包括用于接收像素数据的前端模块。设置单元耦合到前端模块并产生参数系数。光栅单元耦合到设置单元并产生步进信息。虚拟纹理阵列引擎基于参数系数和步进信息对像素数据进行纹理和颜色化。还提供了适用于处理从虚拟纹理化阵列引擎接收的纹理和彩色像素数据的像素引擎。

5. 发明授权

US07797258B1 Graphics system transposer read scheduler 有权
标题翻译：图形系统转换器读调度器
公开(公告)号：US07797258B1
公开(公告)日：2010-09-14
申请号：US11556141
申请日：2006-11-02
申请人： James C. Bowman , Dane T. Mrazek , Sameer M. Gauria
发明人： James C. Bowman , Dane T. Mrazek , Sameer M. Gauria
IPC分类号： G06E1/00 , G06E3/00 , G06F15/18 , G06G7/00 , G06T1/00 , G06T15/00
CPC分类号： G06T1/20
摘要： A graphics system includes a transposer. A read scheduler utilizes a minimum cost analysis to schedule a read transfer order for the transposer to minimize the total number of passes required to process a set of input vectors.
摘要翻译：图形系统包括一个转换器。读调度器利用最小成本分析来调度转移器的读传输顺序，以最小化处理一组输入向量所需的总次数。

6. 发明授权

US08237725B1 Vertex cache map mode for per-vertex state changes 有权
标题翻译：顶点状态改变的顶点缓存映射模式
公开(公告)号：US08237725B1
公开(公告)日：2012-08-07
申请号：US11935239
申请日：2007-11-05
申请人： James C. Bowman , Dane T. Mrazek , Sameer M. Gauria
发明人： James C. Bowman , Dane T. Mrazek , Sameer M. Gauria
IPC分类号： G09G5/36
CPC分类号： G06T15/005 , G06T2210/52
摘要： A vertex cache within a graphics processor is configured to operate as a conventional round-robin streaming cache when per-vertex state changes are not used and is configured to operate as a random access storage buffer when per-vertex state changes are used. Batches of vertices that define primitives and state changes are output to parallel processing units for processing according to vertex shader program. In addition to allowing per-vertex state changes, the vertex cache is configured to store vertices for primitive topologies that use anchor points, such as triangle strips, line loops, and polygons.
摘要翻译：图形处理器中的顶点高速缓存被配置为当不使用每顶点状态改变时作为常规循环流缓存操作，并且当使用每顶点状态改变时被配置为作为随机存取存储缓冲器操作。定义基元和状态变化的顶点批次将输出到并行处理单元，以根据顶点着色器程序进行处理。除了允许每顶点状态改变之外，顶点缓存被配置为存储使用锚点的原始拓扑的顶点，例如三角形条，线环和多边形。

7. 发明授权

US07755631B1 Transposition structures and methods to accommodate parallel processing in a graphics processing unit (“GPU”) 有权
标题翻译：用于在图形处理单元（“GPU”）中适应并行处理的转置结构和方法
公开(公告)号：US07755631B1
公开(公告)日：2010-07-13
申请号：US11552350
申请日：2006-10-24
申请人： Dane T. Mrazek , Sameer M. Gauria , James C. Bowman
发明人： Dane T. Mrazek , Sameer M. Gauria , James C. Bowman
IPC分类号： G06F15/00
CPC分类号： G06T1/00
摘要： Disclosed are an apparatus, a method, a programmable graphics processing unit (“GPU”), a computer device, and a computer medium to facilitate, among other things, the generation of parallel data streams to effect parallel processing in at least a portion of a graphics pipeline of a GPU. In one embodiment, an input of the apparatus receives graphics elements in a data stream of graphics elements. The graphics pipeline can use the graphics elements to form computer-generated images. The apparatus also can include a transposer configured to produce parallel attribute streams. Each of the parallel attribute streams includes a type of attribute common to the graphics elements. In one embodiment, the transposer can be configured to convert at least a portion of the graphics pipeline from a single data stream to multiple data streams (e.g., executable by multiple threads of execution) while reducing the memory size requirements to implement such a conversion.
摘要翻译：公开了一种装置，方法，可编程图形处理单元（“GPU”），计算机设备和计算机介质，以便促进并行数据流的产生，以在至少一部分 GPU的图形流水线。在一个实施例中，设备的输入接收图形元素的数据流中的图形元素。图形管线可以使用图形元素来形成计算机生成的图像。该装置还可以包括被配置为产生并行属性流的转置器。每个并行属性流包括图形元素共有的属性类型。在一个实施例中，转置器可以被配置为将图形流水线的至少一部分从单个数据流转换为多个数据流（例如，由多个执行线程执行），同时减少了实现这种转换的存储器大小要求。

8. 发明授权

US07796137B1 Enhanced tag-based structures, systems and methods for implementing a pool of independent tags in cache memories 有权
标题翻译：增强的基于标签的结构，用于在高速缓冲存储器中实现独立变量池的系统和方法
公开(公告)号：US07796137B1
公开(公告)日：2010-09-14
申请号：US11552415
申请日：2006-10-24
申请人： Dane T. Mrazek , Sameer M. Gauria , James C. Bowman
发明人： Dane T. Mrazek , Sameer M. Gauria , James C. Bowman
IPC分类号： G09G5/36 , G06F12/08
CPC分类号： G06F12/0895 , G06F12/0864
摘要： Disclosed are an apparatus, a system, a method, a graphics processing unit (“GPU”), a computer device, and a computer medium to implement a pool of independent enhanced tags to, among other things, decouple a dependency between tags and cachelines. In one embodiment, an enhanced tag-based cache structure includes a tag repository configured to maintain a pool of enhanced tags. Each enhanced tag can have a match portion configured to form an association between the enhanced tag and an incoming address. Also, an enhanced tag can have a data locator portion configured to locate a cacheline in the cache in response to the formation of the association. The data locator portion enables the enhanced tag to locate multiple cachelines. Advantageously, the enhanced tag-based cache structure can be formed to adjust the degree of reusability of the enhanced tags independent from the degree of latency tolerance for the cacheline repository.
摘要翻译：公开了一种装置，系统，方法，图形处理单元（GPU），计算机设备和计算机介质，以实现独立增强标签池，以便除其他之外，分离标签和高速缓存行之间的依赖关系。在一个实施例中，增强的基于标签的高速缓存结构包括被配置为维护增强标签池的标签库。每个增强标签可以具有匹配部分，其被配置为在增强标签和传入地址之间形成关联。此外，增强标签可以具有配置为响应于关联的形成而在高速缓存中定位高速缓存行的数据定位器部分。数据定位器部分使增强标签能够定位多个高速缓存线。有利地，可以形成增强的基于标签的高速缓存结构，以独立于高速缓存线库的延迟容忍度来调整增强标签的可重用性的程度。

9. 发明授权

US07701459B1 Primitive oriented assembly for parallel vertex/geometry processing 有权
标题翻译：平行顶点/几何处理的原始定向装配
公开(公告)号：US07701459B1
公开(公告)日：2010-04-20
申请号：US11556525
申请日：2006-11-03
申请人： Dane T. Mrazek , James C. Bowman , Sameer M. Gauria
发明人： Dane T. Mrazek , James C. Bowman , Sameer M. Gauria
IPC分类号： G06F15/80 , G06T17/00 , G06F13/00
CPC分类号： G06T15/005 , G06T2210/52
摘要： A graphics system has parallel processing units that do not share vertex information. The graphics system constructs independent batches of work for the parallel processing units in which each batch of work has a list of vertices for a set of primitives.
摘要翻译：图形系统具有不共享顶点信息的并行处理单元。图形系统为并行处理单元构建独立的工作批次，其中每批工作都具有一组基元的顶点列表。

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