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1. 发明授权

US08719502B2 Adaptive self-repairing cache 有权
标题翻译：自适应自修复缓存
公开(公告)号：US08719502B2
公开(公告)日：2014-05-06
申请号：US13436758
申请日：2012-03-30
申请人： Christopher B. Wilkerson , Alaa R. Alameldeen , Jaydeep P. Kulkarni
发明人： Christopher B. Wilkerson , Alaa R. Alameldeen , Jaydeep P. Kulkarni
IPC分类号： G06F12/00
CPC分类号： G06F12/0802 , G06F2212/1032 , G06F2212/604 , Y02D10/13
摘要： A method for operating a cache that includes both robust cells and standard cells may include receiving a data to be written to the cache, determining whether a type of the data is unmodified data or modified data, and writing the data to robust cells or standard cells as a function of the type of the data. A processor includes a core that includes a cache including both robust cells and standard cells for receiving data, wherein the data is written to robust cells or standard cells as a function of whether a type of the data is determined to be unmodified data or modified data.
摘要翻译：用于操作包括鲁棒单元和标准单元的高速缓存的方法可以包括接收要写入高速缓存的数据，确定数据类型是未修改数据还是修改数据，以及将数据写入鲁棒单元或标准单元作为数据类型的函数。处理器包括核心，其包括包括鲁棒单元和用于接收数据的标准单元的高速缓存，其中根据是否将数据类型确定为未修改数据或修改数据，将数据写入鲁棒单元或标准单元。

2. 发明申请

US20150095918A1 SYSTEM AND METHOD FOR THREAD SCHEDULING ON RECONFIGURABLE PROCESSOR CORES 有权
标题翻译：用于可重构加工器线上的螺纹调度的系统和方法
公开(公告)号：US20150095918A1
公开(公告)日：2015-04-02
申请号：US14040142
申请日：2013-09-27
申请人： Alaa R. Alameldeen , Christopher B. Wilkerson , Eugene Gorbatov , Zeshan A. Chishti
发明人： Alaa R. Alameldeen , Christopher B. Wilkerson , Eugene Gorbatov , Zeshan A. Chishti
IPC分类号： G06F9/50 , G06F12/08
CPC分类号： G06F12/0811 , G06F9/5061 , G06F12/0842 , G06F2209/5012 , Y02D10/13 , Y02D10/22 , Y02D10/36
摘要： Systems and methods for efficiently utilizing reconfigurable processor cores. An example processing system includes, for example, a control register comprising a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and dynamic core reallocation logic to temporarily merge a first processor core and a second processor core to speed execution of a first thread executed on the first processor core responsive to determining that a second thread executed on the second processor core has completed execution prior to a quantum associated with the second thread being reached and to determining that the inhibit bits indicate that the first and second cores may be merged.
摘要翻译：有效利用可重构处理器核心的系统和方法。示例性处理系统包括例如包括多个禁止位的控制寄存器，每个禁止位指示是否允许相应的处理器核与其他处理器内核合并; 以及动态核心重新分配逻辑，用于临时合并第一处理器核心和第二处理器核心，以响应于确定在第二处理器核心上执行的第二线程在量化之前已经完成执行，以加速在第一处理器核心上执行的第一线程的执行与第二线程相关联并且确定禁止比特指示第一和第二核可以被合并。

3. 发明申请

US20130326263A1 DYNAMICALLY ALLOCATABLE MEMORY ERROR MITIGATION 有权
标题翻译：动态的内存不正确的缓解
公开(公告)号：US20130326263A1
公开(公告)日：2013-12-05
申请号：US13485474
申请日：2012-05-31
申请人： Alaa R. Alameldeen , Ilya Wagner , Zeshan A. Chishti , Wei Wu , Christopher B. Wilkerson
发明人： Alaa R. Alameldeen , Ilya Wagner , Zeshan A. Chishti , Wei Wu , Christopher B. Wilkerson
IPC分类号： G06F11/20
CPC分类号： G06F11/27 , G06F11/1048 , G06F11/2205
摘要： Embodiments include a method and system of dynamically allocatable memory error mitigation. In one embodiment, a system applies an error mitigation mechanism to one of multiple groups of memory units, wherein the one group is in active use during an error test of a second group of memory units. The system deactivates and tests the second group of memory units for errors. In response to detecting an error in a memory unit of the second group, the system applies, to the memory unit of the second group having the error, the error mitigation mechanism for active use. The system then activates the second group of memory units with the error mitigation mechanism applied to the memory unit of the second group having the error.
摘要翻译：实施例包括动态可分配的存储器错误缓解的方法和系统。在一个实施例中，系统将错误缓解机制应用于多组存储器单元中的一组，其中在第二组存储器单元的错误测试期间，一组正在使用。系统停用并测试第二组存储器单元的错误。响应于检测到第二组的存储器单元中的错误，系统向具有错误的第二组的存储器单元应用用于主动使用的错误减轻机制。然后，该系统激活第二组存储器单元，其中将误差减轻机制应用于具有该错误的第二组的存储器单元。

4. 发明授权

US08806285B2 Dynamically allocatable memory error mitigation 有权
标题翻译：动态分配内存错误缓解
公开(公告)号：US08806285B2
公开(公告)日：2014-08-12
申请号：US13485474
申请日：2012-05-31
申请人： Alaa R. Alameldeen , Ilya Wagner , Zeshan A. Chishti , Wei Wu , Christopher B. Wilkerson
发明人： Alaa R. Alameldeen , Ilya Wagner , Zeshan A. Chishti , Wei Wu , Christopher B. Wilkerson
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G06F11/27 , G06F11/1048 , G06F11/2205
摘要： Embodiments include a method and system of dynamically allocatable memory error mitigation. In one embodiment, a system applies an error mitigation mechanism to one of multiple groups of memory units, wherein the one group is in active use during an error test of a second group of memory units. The system deactivates and tests the second group of memory units for errors. In response to detecting an error in a memory unit of the second group, the system applies, to the memory unit of the second group having the error, the error mitigation mechanism for active use. The system then activates the second group of memory units with the error mitigation mechanism applied to the memory unit of the second group having the error.
摘要翻译：实施例包括动态可分配的存储器错误缓解的方法和系统。在一个实施例中，系统将错误缓解机制应用于多组存储器单元中的一组，其中在第二组存储器单元的错误测试期间，一组正在使用。系统停用并测试第二组存储器单元的错误。响应于检测到第二组的存储器单元中的错误，系统向具有错误的第二组的存储器单元应用用于主动使用的错误减轻机制。然后，该系统激活第二组存储器单元，其中将误差减轻机制应用于具有该错误的第二组的存储器单元。

5. 发明申请

US20140149822A1 SELECTIVE ERROR CORRECTION IN MEMORY TO REDUCE POWER CONSUMPTION 有权
标题翻译：存储器中的选择性错误校正降低功耗
公开(公告)号：US20140149822A1
公开(公告)日：2014-05-29
申请号：US13688028
申请日：2012-11-28
申请人： Christopher B. Wilkerson , Alaa R. Alameldeen , Shih-Lien L. Lu
发明人： Christopher B. Wilkerson , Alaa R. Alameldeen , Shih-Lien L. Lu
IPC分类号： G06F11/08
CPC分类号： G06F11/08 , G06F11/1052
摘要： Embodiments of apparatus, methods, systems, and devices are described herein for selective error correction in memory with multiple operation modes. In various embodiments, an error correction block (e.g., of a memory controller) may be configured to perform error correction on data read from a first portion of a memory based on a corresponding error correction code read from a second portion of the memory, and to calculate and store the error correction code. A control block coupled to the error correction block may be configured to selectively enable/disable the error correction block to perform the error correction, and to calculate and store the error correction code, based at least in part on a current operation mode of the memory.
摘要翻译：本文描述了用于具有多种操作模式的存储器中的选择性误差校正的装置，方法，系统和装置的实施例。在各种实施例中，错误校正块（例如，存储器控制器）可以被配置为基于从存储器的第二部分读取的对应的纠错码对存储器的第一部分读取的数据执行纠错，以及计算和存储纠错码。耦合到纠错块的控制块可以被配置为至少部分地基于存储器的当前操作模式来选择性地启用/禁用纠错块来执行纠错，并且计算和存储纠错码。

6. 发明授权

US08640005B2 Method and apparatus for using cache memory in a system that supports a low power state 有权
标题翻译：在支持低功率状态的系统中使用高速缓冲存储器的方法和装置
公开(公告)号：US08640005B2
公开(公告)日：2014-01-28
申请号：US12785182
申请日：2010-05-21
申请人： Christopher B. Wilkerson , Alaa R. Alameldeen , Zeshan A. Chishti , Dinesh Somasekhar , Wei Wu , Shih-Lien Lu
发明人： Christopher B. Wilkerson , Alaa R. Alameldeen , Zeshan A. Chishti , Dinesh Somasekhar , Wei Wu , Shih-Lien Lu
IPC分类号： G11C29/00
CPC分类号： G06F11/1064
摘要： A cache memory system uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. In an embodiment, error correction logic may include a first error correction logic to determine a number of errors in data that is stored in a cache line of a cache memory, and a second error correction logic to receive the data from the first error correction logic if the number of errors is determined to be greater than one and to perform error correction responsive to receipt of the data. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state. Other embodiments are described and claimed.
摘要翻译：高速缓冲存储器系统使用具有低存储和复杂度开销的多位错误校正码（ECC）。在一个实施例中，纠错逻辑可以包括：第一纠错逻辑，用于确定存储在高速缓存存储器的高速缓存行中的数据中的错误数;以及第二纠错逻辑，用于从第一纠错逻辑接收数据如果错误的数量被确定为大于1，并且响应于数据的接收执行错误校正。高速缓冲存储器系统可以在非常低的空闲功率下操作，而不会由于状态的损失而急剧增加到空闲功率状态的转换等待时间。描述和要求保护其他实施例。

7. 发明授权

US06931490B2 Set address correlation address predictors for long memory latencies 失效
标题翻译：设置长内存延迟的地址相关地址预测变量
公开(公告)号：US06931490B2
公开(公告)日：2005-08-16
申请号：US09738088
申请日：2000-12-15
申请人： Wayne A. Wong , Christopher B. Wilkerson
发明人： Wayne A. Wong , Christopher B. Wilkerson
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： Set address correlation correlates between addresses belonging to a common address set. Addresses are grouped into address sets and correlations are created between addresses by set. The correlations are used to predict future addresses based on current addresses.
摘要翻译：设置地址相关性在属于公共地址集的地址之间相关。地址被分组成地址集，并且通过集合在地址之间创建相关性。相关性用于根据当前地址预测未来地址。

8. 发明授权

US06785797B2 Address predicting apparatus and methods 有权
标题翻译：地址预测装置和方法
公开(公告)号：US06785797B2
公开(公告)日：2004-08-31
申请号：US09741371
申请日：2000-12-19
申请人： Wayne A. Wong , Christopher B. Wilkerson
发明人： Wayne A. Wong , Christopher B. Wilkerson
IPC分类号： G06F1206
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： Apparatus and methods for addressing predicting useful in high-performance computing systems. The present invention provides novel correlation prediction tables. In one embodiment, correlation prediction tables of the present invention contain an entered key for each successor value entered into the correlation table. In a second embodiment, correlation prediction tables of the present invention utilize address offsets for both the entered keys and entered successor values.
摘要翻译：用于寻址预测在高性能计算系统中有用的装置和方法。本发明提供了新的相关预测表。在一个实施例中，本发明的相关预测表包含输入到相关表中的每个后续值的输入密钥。在第二实施例中，本发明的相关预测表利用输入的键和输入的后继值的地址偏移。

9. 发明授权

US06662273B1 Least critical used replacement with critical cache 失效
标题翻译：使用关键缓存的最小关键使用替换
公开(公告)号：US06662273B1
公开(公告)日：2003-12-09
申请号：US09676522
申请日：2000-09-29
申请人： Christopher B. Wilkerson , Srikanth T. Srinivasan , Dz-ching Ju
发明人： Christopher B. Wilkerson , Srikanth T. Srinivasan , Dz-ching Ju
IPC分类号： G06F1200
CPC分类号： G06F12/122 , G06F12/0862 , G06F12/0888 , G06F12/121
摘要： The critical cache tracks a critical score for each cache line in the critical cache. On cache hits, the critical score of the hit cache line is incremented by an instance score assigned to the data request. On cache misses, data may be retrieved from main memory without allocating a cache line into the critical cache, in which case the instance score is subtracted from the critical scores of all cache lines in the cache. Alternatively on a cache miss, the cache line with the smallest critical score is removed from the cache. The smallest critical score is then subtracted from each cache line in the critical cache. A new cache line is allocated that satisfies the data request, and the new cache line is given the instance score of the data request as a critical score.
摘要翻译：关键缓存跟踪关键缓存中每个缓存行的关键分数。在缓存命中时，命中缓存行的临界得分增加了分配给数据请求的实例得分。在缓存未命中时，可以从主存储器检索数据，而不将高速缓存行分配到关键高速缓存中，在这种情况下，从缓存中的所有高速缓存行的关键分数中减去实例分数。或者在缓存未命中时，从缓存中移除具有最小关键分数的高速缓存行。然后从关键缓存中的每个缓存行中减去最小的关键分数。分配满足数据请求的新的高速缓存行，并且将新的高速缓存行作为关键分数给出数据请求的实例分数。

10. 发明申请

US20150149714A1 CONSTRAINING PREFETCH REQUESTS TO A PROCESSOR SOCKET 有权
标题翻译：约束对处理器插座的预先要求
公开(公告)号：US20150149714A1
公开(公告)日：2015-05-28
申请号：US14090056
申请日：2013-11-26
申请人： Seth H. Pugsley , Robert L. Scott , Zeshan A. Chishti , Peng-Fei Chuang , Khun Ban , Christopher B. Wilkerson , Shih-Lien L. Lu , Kingsum Chow
发明人： Seth H. Pugsley , Robert L. Scott , Zeshan A. Chishti , Peng-Fei Chuang , Khun Ban , Christopher B. Wilkerson , Shih-Lien L. Lu , Kingsum Chow
IPC分类号： G06F12/08 , G11C11/406
CPC分类号： G06F12/0862 , G06F8/4442 , G06F12/0811 , G06F12/0897 , G06F2212/602 , Y02D10/13
摘要： In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括具有一个或多个执行单元的至少一个核，第一高速缓冲存储器和第一高速缓存控制逻辑。第一高速缓存控制逻辑可以被配置为生成预取第一数据的第一预取请求，其中如果第一数据不存在于耦合到第一高速缓存存储器的第二高速缓冲存储器中，则该请求将被中止。描述和要求保护其他实施例。

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