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    • 7. 发明授权
    • Processor-controlled timing generator for multiple image sensors
    • 用于多个图像传感器的处理器控制定时发生器
    • US07557849B2
    • 2009-07-07
    • US10963494
    • 2004-10-11
    • Feng F. PanYasu NoguchiYoung Kim
    • Feng F. PanYasu NoguchiYoung Kim
    • H04N3/14H04N5/335
    • H04N5/335
    • A versatile analog front end and timing generator (AFE/TG) integrated circuit is capable of supplying horizontal and vertical timing signals to a large number of disparate image sensors. In a first novel aspect, the AFE/TG includes an output mode wherein multiple identical AFE/TGs output digitized sensor data to a single digital image processor (DIP) without intervening multiplexing circuitry. In a second novel aspect, the AFE/TG includes a processor that executes a program. Execution of the program controls the detailed timing of horizontal and vertical timing signals output from the AFE/TG. At boot time, the program is loaded into the AFE/TG via a serial bus. In a third novel aspect, the processor is clocked by a clock signal with a relatively long clock period. A DLL and associated set/reset circuitry allows the processor to generate and control timing signals with a resolution substantially greater than clock period of the processor.
    • 通用的模拟前端和定时发生器(AFE / TG)集成电路能够向大量不同的图像传感器提供水平和垂直定时信号。 在第一个新颖的方面,AFE / TG包括输出模式,其中多个相同的AFE / TG将数字化的传感器数据输出到单个数字图像处理器(DIP),而不需要插入多路复用电路。 在第二个新颖的方面,AFE / TG包括执行程序的处理器。 程序的执行控制从AFE / TG输出的水平和垂直定时信号的详细时序。 在引导时,程序通过串行总线加载到AFE / TG中。 在第三个新颖的方面,处理器由具有较长时钟周期的时钟信号计时。 DLL和相关联的设置/复位电路允许处理器以比处理器的时钟周期大得多的分辨率产生和控制定时信号。