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1. 发明授权

US06985431B1 Network switch and components and method of operation 有权
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US06985431B1
公开(公告)日：2006-01-10
申请号：US09384692
申请日：1999-08-27
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Fabrice Jean Verplanken , Brian Alan Youngman
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Fabrice Jean Verplanken , Brian Alan Youngman
IPC分类号： H04Q11/04
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
摘要翻译：一种网络交换装置，这种装置的组件，以及操作这样的装置的方法，其中通过控制点和形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。控制点和接口处理器一起形成一个网络处理器，能够在执行指导网络中的数据流的指令的情况下与包括可选交换结构设备在内的其他元件协作。

2. 发明授权

US07620048B2 Network switch and components and method of operation 失效
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US07620048B2
公开(公告)日：2009-11-17
申请号：US11152419
申请日：2005-06-14
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
IPC分类号： H04L12/26 , H04L12/66 , G06F15/16
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： An apparatus is disclosed for transporting control information in a communications system. The apparatus comprises a network processor, a control point processor operatively coupled to the network processor, and a guided frame generated by the control point processor. The guided frame comprises a first section in which frame control information is placed and is used by the network processor to update at least one control register within the network processor; a second section carrying correlators assigned by the control point processor to correlate guided frame responses with their requests; a third section carrying one or a sequence of guided commands; and an End delimiter guided command.
摘要翻译：公开了用于在通信系统中传送控制信息的装置。该装置包括网络处理器，可操作地耦合到网络处理器的控制点处理器以及由控制点处理器生成的引导帧。引导帧包括其中放置帧控制信息的第一部分，并且被网络处理器用于更新网络处理器内的至少一个控制寄存器; 第二部分，承载由控制点处理器分配的相关器，以将引导的帧响应与其请求相关联; 第三部分承载一个或一系列指导命令; 和一个结束分隔符引导命令。

3. 发明授权

US07590057B2 Network switch and components and method of operation 有权
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US07590057B2
公开(公告)日：2009-09-15
申请号：US11152453
申请日：2005-06-14
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
IPC分类号： H04L12/26 , H04L12/66 , G06F15/16
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A control sub system, a plurality of interface processors, a plurality of media interfaces a plurality of queues are operatively coupled and responsive to a control signal to move data from a memory to a selected one of the plurality of queues.
摘要翻译：控制子系统，多个接口处理器，多个媒体接口，多个队列可操作地耦合并且响应于控制信号将数据从存储器移动到多个队列中的所选择的一个队列。

4. 发明授权

US07257616B2 Network switch and components and method of operation 失效
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US07257616B2
公开(公告)日：2007-08-14
申请号：US11152119
申请日：2005-06-14
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
IPC分类号： H04L12/28
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
摘要翻译：一种网络交换装置，这种装置的组件，以及操作这样的装置的方法，其中通过控制点和形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。控制点和接口处理器一起形成一个网络处理器，能够在执行指导网络中的数据流的指令的情况下与包括可选交换结构设备在内的其他元件协作。

5. 发明授权

US06760743B1 Instruction memory system for multi-processor environment and disjoint tasks 有权
标题翻译：指令存储系统，用于多处理器环境和不相交任务
公开(公告)号：US06760743B1
公开(公告)日：2004-07-06
申请号：US09477757
申请日：2000-01-04
申请人： Marco C. Heddes , Mark Anthony Rinaldi , Brian Alan Youngman
发明人： Marco C. Heddes , Mark Anthony Rinaldi , Brian Alan Youngman
IPC分类号： G06F900
CPC分类号： G06F9/3802 , G06F9/3851
摘要： An instruction memory system is shared by a plurality of processors and the system utilizes an increased bandwidth to support the combined number of processors. The total instruction address space is divided into code segments according to the disjoint tasks to be performed. The instruction codes of each processor are consolidated into one copy for control instructions and duplicate copies for other disjoint tasks such as inbound requests and outbound requests that have greater processor contention. Interleaving of the memory arrays for certain disjoint tasks serves to provide a larger number of instructions for these tasks. The system utilizes arbiters to receive all disjoint tasks and to control multiplexors that send addresses to memory arrays.
摘要翻译：指令存储器系统由多个处理器共享，并且系统利用增加的带宽来支持组合的处理器数量。总指令地址空间根据要执行的不相交任务分为代码段。每个处理器的指令代码被合并到一个副本中，用于控制指令和其他不相交任务的重复副本，例如具有更大处理器争用的入站请求和出站请求。用于某些不相交任务的存储器阵列的交织用于为这些任务提供更多数量的指令。该系统利用仲裁器接收所有不相交的任务，并控制向存储器阵列发送地址的多路复用器。

6. 发明授权

US07284260B2 Method and apparatus for bit vector array 失效
标题翻译：位向量阵列的方法和装置
公开(公告)号：US07284260B2
公开(公告)日：2007-10-16
申请号：US10356126
申请日：2003-01-31
申请人： Paul John Hilts , Brian Alan Youngman
发明人： Paul John Hilts , Brian Alan Youngman
IPC分类号： H04N7/173
CPC分类号： H04N7/17309 , H04L12/40013 , H04L12/4135 , H04L12/44 , H04L69/12 , H04L69/324 , H04N7/173 , H04N21/239 , H04N21/437 , H04N21/6168
摘要： A bit vector array apparatus provides a high speed method for processing network transmission controls. Complex data structures for controlling network access are represented in the simplest possible form as single bit vector elements. The bit vector elements are combined into bit vectors comprised of 32 single bit vector elements. The bit vectors are processed in parallel in the bit vector array apparatus, which is comprised of special-purpose bit manipulation functions to expedite the processing.
摘要翻译：位向量阵列装置提供用于处理网络传输控制的高速方法。用于控制网络访问的复杂数据结构以最简单的可能形式表示为单个位向量元素。比特向量元素被组合成由32个单比特向量元素组成的比特向量。比特矢量在比特矢量阵列装置中并行处理，由特殊的比特操作功能组成，以加快处理速度。

7. 发明授权

US6049837A Programmable output interface for lower level open system interconnection architecture 失效
标题翻译：可编程输出接口，用于较低级别的开放系统互连架构
公开(公告)号：US6049837A
公开(公告)日：2000-04-11
申请号：US987189
申请日：1997-12-08
申请人： Brian Alan Youngman
发明人： Brian Alan Youngman
IPC分类号： H04L12/28 , G06F13/18 , G06F13/00 , G06F15/16
CPC分类号： H04L12/2801
摘要： A programmable output interface in an Open System Interconnection (OSI) enables a Media Access (MAC) Layer to access a variety of Physical (PHY) Layer implementations without redesign of the interface. The programmable interface includes a control signal generator; an output clock gating generator, and an output polarity control device coupled to the PHY layer. The interface receives media access Start; media access Done signals; a Data Rate clock signal and a data signal. The control signal generator provides control signals for the physical layer components via the polarity control device. The active signal polarity and the relative timing of the control signals are controlled by programmable registers. The output clock gating generator provides clock signals to the physical layer components via the polarity control in response to the Start; Done and Data Rate signals. The output generator clock includes programmable interval registers for the various frame intervals including a User Pause Interval (UPI); Preamble Interval (PI); User Send Interval (USI), etc. The polarity control provides the correct signal polarity for each control, clock, and data signal.
摘要翻译：开放系统互连（OSI）中的可编程输出接口使媒体访问（MAC）层可以访问各种物理层（PHY）层，而无需重新设计接口。可编程接口包括控制信号发生器; 输出时钟选通发生器，以及耦合到PHY层的输出极性控制装置。接口接收媒体访问开始; 媒体访问完成信号; 数据速率时钟信号和数据信号。控制信号发生器通过极性控制装置提供物理层组件的控制信号。有源信号极性和控制信号的相对定时由可编程寄存器控制。输出时钟选通发生器响应于启动通过极性控制向物理层组件提供时钟信号; 完成和数据速率信号。输出发生器时钟包括用于各种帧间隔的可编程间隔寄存器，包括用户暂停间隔（UPI）; 前导码间隔（PI）; 用户发送间隔（USI）等。极性控制为每个控制，时钟和数据信号提供正确的信号极性。

8. 发明授权

US5719864A Logical channel resolution in asynchronous transmission mode communication systems 失效
标题翻译：异步传输模式通信系统中的逻辑信道分辨率
公开(公告)号：US5719864A
公开(公告)日：1998-02-17
申请号：US513711
申请日：1995-08-11
申请人： Ryan Lance Badger , Vernon Roberts Norman , Brian Alan Youngman
发明人： Ryan Lance Badger , Vernon Roberts Norman , Brian Alan Youngman
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/28
CPC分类号： H04L49/3081 , H04Q11/0478 , H04L2012/5614 , H04L2012/5619
摘要： An asynchronous transmission mode data cell header includes virtual channel and virtual path identifiers which are resolved into logical channel identifiers at the user interface by two table lookup operations. The virtual path identifier is used to access a virtual path table entry having a variable length pointer value buffered out to a fixed length field by zeros with a binary one at the boundary position. Using the binary one as a marker, the pointer field is extracted and concatenated with a base register value and the lower order bits of the virtual channel identifier, corresponding to the bit position of the binary one marker, to provide an index into a logical channel identifier table. The logical channel identifier is used to associate the data cell attached to that header with the appropriate user data stream.
摘要翻译：异步传输模式数据单元报头包括虚拟通道和虚拟路径标识符，其通过两个表查找操作在用户界面处被解析为逻辑信道标识符。虚拟路径标识符用于访问虚拟路径表条目，该虚拟路径表条目具有通过在边界位置处具有二进制值的零来缓冲到固定长度字段的可变长度指针值。使用二进制一个作为标记，指针字段被提取并与基本寄存器值和虚拟信道标识符的低位比特相对应，与二进制一个标记的比特位置相对应，以向逻辑信道提供索引标识符表。逻辑信道标识符用于将附加到该报头的数据信元与适当的用户数据流相关联。

9. 发明授权

US06681315B1 Method and apparatus for bit vector array 失效
标题翻译：位向量阵列的方法和装置
公开(公告)号：US06681315B1
公开(公告)日：2004-01-20
申请号：US08980070
申请日：1997-11-26
申请人： Paul John Hilts , Brian Alan Youngman
发明人： Paul John Hilts , Brian Alan Youngman
IPC分类号： G06F1500
CPC分类号： H04N7/17309 , H04L12/40013 , H04L12/4135 , H04L12/44 , H04L69/12 , H04L69/324 , H04N7/173 , H04N21/239 , H04N21/437 , H04N21/6168
摘要： A bit vector array apparatus provides a high speed method for processing network transmission controls. Complex data structures for controlling network access are represented in the simplest possible form as single bit vector elements. The bit vector elements are combined into bit vectors comprised of 32 single bit vector elements. The bit vectors are processed in parallel in the bit vector array apparatus, which is comprised of special-purpose bit manipulation functions to expedite the processing.
摘要翻译：位向量阵列装置提供用于处理网络传输控制的高速方法。用于控制网络访问的复杂数据结构以最简单的可能形式表示为单个位向量元素。比特向量元素被组合成由32个单比特向量元素组成的比特向量。比特矢量在比特矢量阵列装置中并行处理，由特殊的比特操作功能组成，以加快处理速度。

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