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1. 发明授权

US08373228B2 Semiconductor transistor device structure with back side source/drain contact plugs, and related manufacturing method 有权
标题翻译：具有背面源极/漏极接触插头的半导体晶体管器件结构及相关制造方法
公开(公告)号：US08373228B2
公开(公告)日：2013-02-12
申请号：US12687607
申请日：2010-01-14
申请人： Bin Yang , Rohit Pal , Michael Hargrove
发明人： Bin Yang , Rohit Pal , Michael Hargrove
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/845 , H01L23/485 , H01L27/12 , H01L27/1211
摘要： A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.
摘要翻译：此处提供制造具有背面导电插头的半导体器件的方法。该方法通过形成覆盖绝缘体上半导体（SOI）衬底的栅极结构开始。 SOI衬底具有支撑层，覆盖在支撑层上的绝缘层，覆盖绝缘层的有源半导体区域和有源半导体区域外侧的隔离区域。栅极结构的第一部分形成在隔离区域的上方，栅极结构的第二部分形成在有源半导体区域的上方。该方法通过在有源半导体区域中形成源极/漏极区域继续，然后从SOI衬底去除支撑层。接下来，该方法形成用于栅极结构和源极/漏极区域的导电插塞，其中每个导电插塞穿过绝缘层。

2. 发明授权

US08217463B2 Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods 有权
标题翻译：用于在由这种方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法
公开(公告)号：US08217463B2
公开(公告)日：2012-07-10
申请号：US13021403
申请日：2011-02-04
申请人： Rohit Pal , Michael Hargrove , Frank Bin Yang
发明人： Rohit Pal , Michael Hargrove , Frank Bin Yang
IPC分类号： H01L29/66
CPC分类号： H01L29/66651 , H01L21/28123 , H01L21/28194 , H01L21/28247 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.
摘要翻译：提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。制造半导体器件的方法包括提供具有有源区和浅沟槽隔离（STI）区的半导体衬底。在有源区上形成外延层，以在有源区/ STI区界面上的边界中限定一个横向伸出部分。形成具有覆盖在半导体衬底上的第一栅叠层形成层的栅叠层。第一栅极堆叠形成层包括定向沉积以形成刚好在横向突出部分下方的变薄的断裂部分的非保形层的金属栅极形成材料。在形成栅极堆叠的步骤之后，非共形层的第一部分在栅极堆叠中并且第二部分被暴露。减薄断裂部分在随后的蚀刻化学过程中至少部分地隔离第一和第二部分。

3. 发明授权

US08294211B2 Semiconductor transistor device structure with back side gate contact plugs, and related manufacturing method 有权
标题翻译：具有背面栅极接触插头的半导体晶体管器件结构及相关制造方法
公开(公告)号：US08294211B2
公开(公告)日：2012-10-23
申请号：US12687610
申请日：2010-01-14
申请人： Bin Yang , Rohit Pal , Michael Hargrove
发明人： Bin Yang , Rohit Pal , Michael Hargrove
IPC分类号： H01L29/786
CPC分类号： H01L27/12 , H01L21/84 , H01L21/845 , H01L23/485 , H01L27/1211
摘要： A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.
摘要翻译：此处提供制造具有背面导电插头的半导体器件的方法。该方法通过形成覆盖绝缘体上半导体（SOI）衬底的栅极结构开始。 SOI衬底具有支撑层，覆盖在支撑层上的绝缘层，覆盖绝缘层的有源半导体区域和有源半导体区域外侧的隔离区域。栅极结构的第一部分形成在隔离区域的上方，栅极结构的第二部分形成在有源半导体区域的上方。该方法通过在有源半导体区域中形成源极/漏极区域继续，然后从SOI衬底去除支撑层。接下来，该方法形成用于栅极结构和源极/漏极区域的导电插塞，其中每个导电插塞穿过绝缘层。

4. 发明授权

US08026539B2 Metal oxide semiconductor devices having doped silicon-compromising capping layers and methods for fabricating the same 有权
标题翻译：具有掺杂的含硅覆盖层的金属氧化物半导体器件及其制造方法
公开(公告)号：US08026539B2
公开(公告)日：2011-09-27
申请号：US12388094
申请日：2009-02-18
申请人： Michael Hargrove , Frank Bin Yang , Rohit Pal
发明人： Michael Hargrove , Frank Bin Yang , Rohit Pal
IPC分类号： H01L29/76
CPC分类号： H01L21/28088 , H01L21/28079 , H01L21/823842 , H01L21/82385 , H01L29/1054 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.
摘要翻译：提供了用于形成包括半导体衬底的半导体器件的方法。根据示例性实施例，一种方法包括以下步骤：形成覆盖在半导体衬底上的高k电介质层，形成覆盖在高k电介质层上的包含金属的栅极层，形成掺杂的含硅覆盖层含金属的栅极层，以及沉积覆盖掺杂的含硅覆盖层的含硅栅极层。

5. 发明申请

US20100207176A1 Metal oxide semiconductor devices having doped silicon-compromising capping layers and methods for fabricating the same 有权
标题翻译：具有掺杂的含硅覆盖层的金属氧化物半导体器件及其制造方法
公开(公告)号：US20100207176A1
公开(公告)日：2010-08-19
申请号：US12388094
申请日：2009-02-18
申请人： Michael Hargrove , Frank Bin Yang , Rohit Pal
发明人： Michael Hargrove , Frank Bin Yang , Rohit Pal
IPC分类号： H01L29/78 , H01L21/4763
CPC分类号： H01L21/28088 , H01L21/28079 , H01L21/823842 , H01L21/82385 , H01L29/1054 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.
摘要翻译：提供了用于形成包括半导体衬底的半导体器件的方法。根据示例性实施例，一种方法包括以下步骤：形成覆盖在半导体衬底上的高k电介质层，形成覆盖在高k电介质层上的包含金属的栅极层，形成掺杂的含硅覆盖层含金属的栅极层，以及沉积覆盖掺杂的含硅覆盖层的含硅栅极层。

6. 发明授权

US07632727B2 Method of forming stepped recesses for embedded strain elements in a semiconductor device 有权
标题翻译：在半导体器件中形成用于嵌入式应变元件的阶梯式凹陷的方法
公开(公告)号：US07632727B2
公开(公告)日：2009-12-15
申请号：US12119384
申请日：2008-05-12
申请人： Rohit Pal , Frank Bin Yang , Michael Hargrove
发明人： Rohit Pal , Frank Bin Yang , Michael Hargrove
IPC分类号： H01L29/772
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/26586 , H01L21/3065 , H01L29/165 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A method of fabricating a semiconductor transistor device is provided. The fabrication method begins by forming a gate structure overlying a layer of semiconductor material, such as silicon. Then, spacers are formed about the sidewalls of the gate structure. Next, ions of an amorphizing species are implanted into the semiconductor material at a tilted angle toward the gate structure. The gate structure and the spacers are used as an ion implantation mask during this step. The ions form amorphized regions in the semiconductor material. Thereafter, the amorphized regions are selectively removed, resulting in corresponding recesses in the semiconductor material. In addition, the recesses are filled with stress inducing semiconductor material, and fabrication of the semiconductor transistor device is completed.
摘要翻译：提供一种制造半导体晶体管器件的方法。制造方法通过形成覆盖诸如硅的半导体材料层的栅极结构开始。然后，围绕栅极结构的侧壁形成间隔物。接下来，非晶化物质的离子以倾斜的角度注入到栅极结构中。在该步骤中，栅极结构和间隔物用作离子注入掩模。离子在半导体材料中形成非晶化区域。此后，非晶化区域被选择性地去除，从而在半导体材料中产生相应的凹槽。此外，凹部被应力诱导半导体材料填充，并且半导体晶体管器件的制造完成。

7. 发明申请

US20110095341A1 METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED FROM SUCH METHODS 有权
公开(公告)号：US20110095341A1
公开(公告)日：2011-04-28
申请号：US12604281
申请日：2009-10-22
申请人： Rohit Pal , Michael Hargrove , Frank Bin Yang
发明人： Rohit Pal , Michael Hargrove , Frank Bin Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66651 , H01L21/28123 , H01L21/28194 , H01L21/28247 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.

8. 发明授权

US07932143B1 Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods 有权
标题翻译：用于在由这种方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法
公开(公告)号：US07932143B1
公开(公告)日：2011-04-26
申请号：US12604281
申请日：2009-10-22
申请人： Rohit Pal , Michael Hargrove , Frank Bin Yang
发明人： Rohit Pal , Michael Hargrove , Frank Bin Yang
IPC分类号： H01L21/8238
CPC分类号： H01L29/66651 , H01L21/28123 , H01L21/28194 , H01L21/28247 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.
摘要翻译：提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。制造半导体器件的方法包括提供具有有源区和浅沟槽隔离（STI）区的半导体衬底。在有源区上形成外延层，以在有源区/ STI区界面上的边界中限定一个横向伸出部分。形成具有覆盖在半导体衬底上的第一栅叠层形成层的栅叠层。第一栅极堆叠形成层包括定向沉积以形成刚好在横向突出部分下方的变薄的断裂部分的非保形层的金属栅极形成材料。在形成栅极堆叠的步骤之后，非共形层的第一部分在栅极堆叠中并且第二部分被暴露。减薄断裂部分在随后的蚀刻化学过程中至少部分地隔离第一和第二部分。

9. 发明申请

US20090280627A1 METHOD OF FORMING STEPPED RECESSES FOR EMBEDDED STRAIN ELEMENTS IN A SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中形成嵌入式应变元件的步进保持的方法
公开(公告)号：US20090280627A1
公开(公告)日：2009-11-12
申请号：US12119384
申请日：2008-05-12
申请人： Rohit Pal , Frank Bin Yang , Michael Hargrove
发明人： Rohit Pal , Frank Bin Yang , Michael Hargrove
IPC分类号： H01L21/322
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/26586 , H01L21/3065 , H01L29/165 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A method of fabricating a semiconductor transistor device is provided. The fabrication method begins by forming a gate structure overlying a layer of semiconductor material, such as silicon. Then, spacers are formed about the sidewalls of the gate structure. Next, ions of an amorphizing species are implanted into the semiconductor material at a tilted angle toward the gate structure. The gate structure and the spacers are used as an ion implantation mask during this step. The ions form amorphized regions in the semiconductor material. Thereafter, the amorphized regions are selectively removed, resulting in corresponding recesses in the semiconductor material. In addition, the recesses are filled with stress inducing semiconductor material, and fabrication of the semiconductor transistor device is completed.
摘要翻译：提供一种制造半导体晶体管器件的方法。制造方法通过形成覆盖诸如硅的半导体材料层的栅极结构开始。然后，围绕栅极结构的侧壁形成间隔物。接下来，非晶化物质的离子以倾斜的角度注入到栅极结构中。在该步骤中，栅极结构和间隔物用作离子注入掩模。离子在半导体材料中形成非晶化区域。此后，非晶化区域被选择性地去除，从而在半导体材料中产生相应的凹槽。此外，凹部被应力诱导半导体材料填充，并且半导体晶体管器件的制造完成。

10. 发明授权

US07670934B1 Methods for fabricating MOS devices having epitaxially grown stress-inducing source and drain regions 有权
标题翻译：制造具有外延生长的应力诱导源极和漏极区域的MOS器件的方法
公开(公告)号：US07670934B1
公开(公告)日：2010-03-02
申请号：US12359764
申请日：2009-01-26
申请人： Rohit Pal , Frank Bin Yang
发明人： Rohit Pal , Frank Bin Yang
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/84
摘要： Methods of fabricating a semiconductor device on and in a semiconductor substrate having a first region and a second region are provided. In accordance with an exemplary embodiment of the invention, a method comprises forming a first gate stack overlying the first region and a second gate stack overlying the second region, etching into the substrate first recesses and second recesses, the first recesses aligned at least to the first gate stack in the first region, and the second recesses aligned at least to the second gate stack in the second region, epitaxially growing a first stress-inducing monocrystalline material in the first and second recesses, removing the first stress-inducing monocrystalline material from the first recesses, and epitaxially growing a second stress-inducing monocrystalline material in the first recesses, wherein the second stress-inducing monocrystalline material has a composition different from the first stress-inducing monocrystalline material.
摘要翻译：提供了在具有第一区域和第二区域的半导体衬底上和半导体衬底中制造半导体器件的方法。根据本发明的示例性实施例，一种方法包括形成覆盖第一区域的第一栅极堆叠和覆盖第二区域的第二栅极堆叠，蚀刻到衬底中的第一凹陷和第二凹槽，第一凹陷至少对准第一栅极堆叠在第一区域中，并且第二凹陷至少对准第二区域中的第二栅极堆叠，在第一和第二凹槽中外延生长第一应力诱导单晶材料，从第一和第二凹槽中去除第一应力诱导单晶材料第一凹陷，并且在第一凹陷中外延生长第二应力诱导单晶材料，其中第二应力诱导单晶材料具有不同于第一应力诱导单晶材料的组成。

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