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1. 发明授权

US07454832B2 Method of forming metal plate pattern and circuit board 失效
标题翻译：形成金属板图案和电路板的方法
公开(公告)号：US07454832B2
公开(公告)日：2008-11-25
申请号：US11506589
申请日：2006-08-18
申请人： Toyoaki Sakai , Katsuya Fukase
发明人： Toyoaki Sakai , Katsuya Fukase
IPC分类号： H05K3/02
CPC分类号： H05K3/062 , H01L21/4828 , H01L21/4846 , H01L23/49548 , H01L2924/0002 , H05K3/202 , H05K2203/0369 , H05K2203/0597 , H05K2203/1476 , Y10T29/49117 , Y10T29/49155 , Y10T29/49204 , H01L2924/00
摘要： A method of forming a high aspect ratio metal plate pattern or circuit board by multi-stage etching with a metal mask is disclosed. A resist (12) is coated on one or two surfaces of a copper plate (10) and patterned into a resist pattern. A tin plating layer (14) is formed using this resist pattern, and with this tin plating layer as a mask, the copper plate is half etched. By coating, exposing and developing the positive resist (18), the positive resist under the tin plating layer is protected. With the tin plating layer and the protective resist layer as a mask, the half etching is executed again. This process is repeated until the resist and the tin plating layer used as a masking are finally removed to produce a metal pattern (20).
摘要翻译：公开了一种通过金属掩模的多级蚀刻形成高纵横比金属板图案或电路板的方法。抗蚀剂（12）涂覆在铜板（10）的一个或两个表面上并且被图案化成抗蚀剂图案。使用该抗蚀剂图案形成镀锡层（14），以该镀锡层为掩模，对铜板进行半蚀刻。通过涂覆，曝光和显影正性抗蚀剂（18），镀锡层下的正性抗蚀剂得到保护。以镀锡层和保护层为掩模，再次进行半蚀刻。重复该过程，直到最终除去用作掩模的抗蚀剂和锡镀层以产生金属图案（20）。

2. 发明申请

US20080197294A1 MANUFACTURING METHOD OF CIRCUIT BOARD 审中-公开
标题翻译：电路板制造方法
公开(公告)号：US20080197294A1
公开(公告)日：2008-08-21
申请号：US12030543
申请日：2008-02-13
申请人： Toyoaki SAKAI
发明人： Toyoaki SAKAI
IPC分类号： G03F7/20
CPC分类号： G03F7/2051 , H05K3/0082
摘要： An exposure method includes: (a) providing a substrate coated with a photosensitive material on a stage; and (b) applying a spot light beam emitted from a light source to the photosensitive material while moving the stage in accordance with a previously programmed exposure pattern for wiring formation, thereby performing pattern exposure of the photosensitive material. In the exposure method, the spot light beam is controlled so that the spot light beam is formed into an ellipse whose major axis is in a direction perpendicular to a move direction of the stage.
摘要翻译：曝光方法包括：（a）在舞台上提供涂有感光材料的基底; 并且（b）根据用于布线形成的预先编程的曝光图案，将从光源发射的点光束施加到感光材料，同时移动平台，从而执行感光材料的图案曝光。在曝光方法中，控制点光束使得点光束形成为长轴在与舞台的移动方向垂直的方向上的椭圆。

3. 发明申请

US20070042585A1 Method of forming metal plate pattern and circuit board 失效
标题翻译：形成金属板图案和电路板的方法
公开(公告)号：US20070042585A1
公开(公告)日：2007-02-22
申请号：US11506589
申请日：2006-08-18
申请人： Toyoaki Sakai , Katsuya Fukase
发明人： Toyoaki Sakai , Katsuya Fukase
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H05K3/062 , H01L21/4828 , H01L21/4846 , H01L23/49548 , H01L2924/0002 , H05K3/202 , H05K2203/0369 , H05K2203/0597 , H05K2203/1476 , Y10T29/49117 , Y10T29/49155 , Y10T29/49204 , H01L2924/00
摘要： A method of forming a high aspect ratio metal plate pattern or circuit board by multi-stage etching with a metal mask is disclosed. A resist (12) is coated on one or two surfaces of a copper plate (10) and patterned into a resist pattern. A tin plating layer (14) is formed using this resist pattern, and with this tin plating layer as a mask, the copper plate is half etched. By coating, exposing and developing the positive resist (18), the positive resist under the tin plating layer is protected. With the tin plating layer and the protective resist layer as a mask, the half etching is executed again. This process is repeated until the resist and the tin plating layer used as a masking are finally removed to produce a metal pattern (20).
摘要翻译：公开了一种通过金属掩模的多级蚀刻形成高纵横比金属板图案或电路板的方法。抗蚀剂（12）涂覆在铜板（10）的一个或两个表面上并且被图案化成抗蚀剂图案。使用该抗蚀剂图案形成镀锡层（14），以该镀锡层为掩模，对铜板进行半蚀刻。通过涂覆，曝光和显影正性抗蚀剂（18），镀锡层下的正性抗蚀剂得到保护。以镀锡层和保护层为掩模，再次进行半蚀刻。重复该过程，直到最终除去用作掩模的抗蚀剂和锡镀层以产生金属图案（20）。

4. 发明授权

US08143533B2 Method for forming resist pattern, method for producing circuit board, and circuit board 失效
标题翻译：抗蚀剂图案形成方法，电路基板的制造方法以及电路基板
公开(公告)号：US08143533B2
公开(公告)日：2012-03-27
申请号：US12227377
申请日：2006-05-17
申请人： Yasuo Kaneda , Munetoshi Irisawa , Yuji Toyoda , Toyokazu Komuro , Katsuya Fukase , Toyoaki Sakai
发明人： Yasuo Kaneda , Munetoshi Irisawa , Yuji Toyoda , Toyokazu Komuro , Katsuya Fukase , Toyoaki Sakai
IPC分类号： H05K1/03
CPC分类号： H05K3/426 , H05K1/116 , H05K3/002 , H05K3/108 , H05K2201/09545 , H05K2203/0191 , H05K2203/0574 , H05K2203/1184 , H05K2203/1394
摘要： There are provided a method for forming a resist pattern for preparing a circuit board having a landless or small-land-width through-hole(s) to realize a high-density circuit board, a method for producing a circuit board, and a circuit board. A method for forming a resist pattern, comprising the steps of forming a resin layer and a mask layer on a first surface of a substrate having a through-hole(s), and removing the resin layer on the through-hole(s) and on a periphery of the through-hole(s) on the first surface by supplying a resin layer removing solution from a second surface opposite to the first surface of the substrate, and a method for producing a circuit board using the method for forming a resist pattern, and a circuit board.
摘要翻译：提供了一种形成抗蚀剂图案的方法，该抗蚀剂图案用于制备具有无轨或小地平面宽度的通孔的电路板，以实现高密度电路板，生产电路板的方法和电路板。一种形成抗蚀剂图案的方法，包括以下步骤：在具有通孔的基板的第一表面上形成树脂层和掩模层，并且除去通孔上的树脂层和通过从与基板的第一表面相对的第二表面提供树脂层去除溶液，在第一表面的通孔的周边上，以及使用该抗蚀剂形成方法制造电路板的方法图案和电路板。

5. 发明授权

US07679004B2 Circuit board manufacturing method and circuit board 有权
标题翻译：电路板制造方法和电路板
公开(公告)号：US07679004B2
公开(公告)日：2010-03-16
申请号：US10598524
申请日：2005-03-02
申请人： Katsuya Fukase , Toyoaki Sakai , Munetoshi Irisawa , Toyokazu Komuro , Yasuo Kaneda , Masanori Natsuka , Wakana Aizawa
发明人： Katsuya Fukase , Toyoaki Sakai , Munetoshi Irisawa , Toyokazu Komuro , Yasuo Kaneda , Masanori Natsuka , Wakana Aizawa
IPC分类号： H01R12/04 , H05K1/00
CPC分类号： H05K3/064 , H05K1/116 , H05K3/0094 , H05K3/061 , H05K3/065 , H05K3/108 , H05K3/421 , H05K3/427 , H05K2201/09381 , H05K2201/09563 , H05K2201/09581 , H05K2201/098 , H05K2203/0517 , H05K2203/0577 , H05K2203/0582 , H05K2203/1184 , H05K2203/1394
摘要： As means for solving a problem of a positional shift of a land and a hole which is caused by an alignment in the formation of an etching resist layer and a plated resist layer in a method of manufacturing a circuit board, there are provided a method of manufacturing a circuit board including the steps of forming a first resin layer on a surface of an insulating substrate having a conductive layer on the surface and an internal wall of a through hole or/and a non-through hole, forming a second resin layer which is insoluble or slightly soluble in a developing solution for the first resin layer on the first resin layer provided on the surface conductive layer, and removing the first resin layer provided over the hole with the developing solution for the first resin layer, and a method of manufacturing a circuit board including the step of uniformly charging a surface of the first resin layer to induce a potential difference to the first resin layer provided over the hole and the first resin layer provided on the surface conductive layer before forming the second resin layer. Moreover, there is provided a circuit board having a hole with a small positional shift and high precision.
摘要翻译：作为在电路基板的制造方法中解决在形成抗蚀剂层和电镀抗蚀剂层时的取向引起的焊盘和孔的位置偏移的问题的方法，提供了一种方法，制造电路板，包括以下步骤：在表面上具有导电层的绝缘基板的表面上形成第一树脂层和通孔或/或非通孔的内壁，形成第二树脂层，所述第二树脂层在设置在表面导电层上的第一树脂层上的第一树脂层的显影液中不溶或微溶，用第一树脂层的显影液除去设在孔上的第一树脂层，制造电路板，包括对第一树脂层的表面均匀充电以对设置在孔上的第一树脂层引起电位差的步骤，在形成第二树脂层之前，在表面导电层上设置阴极层。此外，提供一种电路板，其具有位置偏移小且精度高的孔。

6. 发明申请

US20070017090A1 Method of forming metal plate pattern and circuit board 审中-公开
标题翻译：形成金属板图案和电路板的方法
公开(公告)号：US20070017090A1
公开(公告)日：2007-01-25
申请号：US11486820
申请日：2006-07-13
申请人： Toyoaki Sakai , Katsuya Fukase
发明人： Toyoaki Sakai , Katsuya Fukase
IPC分类号： H01B13/00 , H05K3/00
CPC分类号： H05K3/064 , C23F1/02 , H01L2924/0002 , H05K3/06 , H05K3/062 , H05K3/202 , H05K2203/0369 , H05K2203/0508 , H05K2203/058 , H05K2203/0597 , H05K2203/1184 , H05K2203/1476 , H05K2203/1572 , Y10T29/49124 , H01L2924/00
摘要： A method of forming a high aspect ratio metal plate pattern and a circuit board by multi-stage etching with a metal mask is disclosed. A resist (12) is coated on one of two surfaces of a copper plate (10) and patterned to form a resist pattern. A tin plating layer (14) is formed using this resist pattern, and with this tin plating layer as a mask, the copper plate is selectively half etched. By coating, exposing and developing the positive resist (18), the side etched portion under the tin plating layer is protected by the positive resist. With the tin plating layer and the protective resist layer as a mask, the half etching is executed again. This process is repeated until the resist and the tin plating layer used as a mask are finally removed to produce a metal pattern (20).
摘要翻译：公开了一种通过金属掩模的多级蚀刻形成高纵横比金属板图案和电路板的方法。抗蚀剂（12）涂覆在铜板（10）的两个表面中的一个上并被图案化以形成抗蚀剂图案。使用该抗蚀剂图案形成锡镀层（14），以该镀锡层为掩模，选择性地对铜板进行半蚀刻。通过涂覆，曝光和显影正性抗蚀剂（18），镀锡层下面的侧蚀刻部分被正性抗蚀剂保护。以镀锡层和保护层为掩模，再次进行半蚀刻。重复该过程，直到最终除去用作掩模的抗蚀剂和锡镀层以产生金属图案（20）。

7. 发明申请

US20090236137A1 Method for Forming Resist Pattern, Method for Producing Circuit Board, and Circuit Board 失效
标题翻译：形成抗蚀剂图案的方法，生产电路板和电路板的方法
公开(公告)号：US20090236137A1
公开(公告)日：2009-09-24
申请号：US12227377
申请日：2006-05-17
申请人： Yasuo Kaneda , Munetoshi Irisawa , Yuji Toyoda , Toyokazu Komuro , Katsuya Fukase , Toyoaki Sakai
发明人： Yasuo Kaneda , Munetoshi Irisawa , Yuji Toyoda , Toyokazu Komuro , Katsuya Fukase , Toyoaki Sakai
IPC分类号： H05K1/11 , G03F7/20
CPC分类号： H05K3/426 , H05K1/116 , H05K3/002 , H05K3/108 , H05K2201/09545 , H05K2203/0191 , H05K2203/0574 , H05K2203/1184 , H05K2203/1394
摘要： There are provided a method for forming a resist pattern for preparing a circuit board having a landless or small-land-width through-hole(s) to realize a high-density circuit board, a method for producing a circuit board, and a circuit board. A method for forming a resist pattern, comprising the steps of forming a resin layer and a mask layer on a first surface of a substrate having a through-hole(s), and removing the resin layer on the through-hole(s) and on a periphery of the through-hole(s) on the first surface by supplying a resin layer removing solution from a second surface opposite to the first surface of the substrate, and a method for producing a circuit board using the method for forming a resist pattern, and a circuit board.
摘要翻译：提供了一种形成抗蚀剂图案的方法，该抗蚀剂图案用于制备具有无轨或小地平面宽度的通孔的电路板，以实现高密度电路板，生产电路板的方法和电路板。一种形成抗蚀剂图案的方法，包括以下步骤：在具有通孔的基板的第一表面上形成树脂层和掩模层，并且除去通孔上的树脂层和通过从与基板的第一表面相对的第二表面提供树脂层去除溶液，在第一表面的通孔的周边上，以及使用该抗蚀剂形成方法制造电路板的方法图案和电路板。

8. 发明申请

US20050124091A1 Process for making circuit board or lead frame 审中-公开
标题翻译：制造电路板或引线框架的工艺
公开(公告)号：US20050124091A1
公开(公告)日：2005-06-09
申请号：US10978521
申请日：2004-11-02
申请人： Katsuya Fukase , Toyoaki Sakai
发明人： Katsuya Fukase , Toyoaki Sakai
IPC分类号： H01L21/48 , H05K3/06 , H05K3/20 , H01L21/44 , H01L21/425 , H01L21/50 , H01L21/82
CPC分类号： H05K3/064 , H01L21/4821 , H01L21/4828 , H01L21/4846 , H05K3/062 , H05K3/202 , H05K2203/0369 , H05K2203/0508 , H05K2203/058 , H05K2203/0597 , H05K2203/1476
摘要： A process for forming a metal pattern comprising the following steps of: (a) half-etching a metal plate from one or respective sides thereof by means of first masking which is positioned on one or respective surfaces of the metal plate; (b) applying positive liquid resist on the half-etched metal plate from one or respective sides of the first masking; (c) exposing the positive liquid resist with light from one or respective sides of the first masking; (d) developing the positive liquid resist in such a manner that unexposed positive liquid resist located under the first masking is protected and exposed, uncured liquid resist is removed; (e) half-etching again the metal plate from one or respective sides thereof by means of second masking composed of the first masking and the protected positive liquid resist; (f) repeating the steps (b) to (e) until a metal pattern is obtained from the metal plate; and (g) removing the first masking, and the second or subsequent masking of the unexposed positive liquid resist, from the metal plate.
摘要翻译：一种用于形成金属图案的方法，包括以下步骤：（a）通过位于金属板的一个或相应表面上的第一掩模从其一侧或两侧半蚀刻金属板; （b）从第一掩模的一个或相应的两侧向半蚀刻的金属板施加正的液体抗蚀剂; （c）用来自第一掩模的一个或相应侧面的光曝光正极液体抗蚀剂; （d）以防止位于第一掩模下面的未曝光的正性液体抗蚀剂被保护和暴露的方式显影出正的液体抗蚀剂，去除未固化的液体抗蚀剂; （e）通过由第一掩模和受保护的正性液体抗蚀剂组成的第二掩模，从其一侧或两侧再次对金属板进行蚀刻; （f）重复步骤（b）至（e），直到从金属板获得金属图案; 和（g）从金属板去除未曝光的正性液体抗蚀剂的第一掩蔽和第二次或随后的掩蔽。

9. 发明申请

US20070181994A1 Circuit board manufacturing method and circuit board 有权
标题翻译：电路板制造方法和电路板
公开(公告)号：US20070181994A1
公开(公告)日：2007-08-09
申请号：US10598524
申请日：2005-03-02
申请人： Katsuya Fukase , Toyoaki Sakai , Munetoshi Irisawa , Toyokazu Komuro , Yasuo Kaneda , Masanori Natsuka , Wakana Aizawa
发明人： Katsuya Fukase , Toyoaki Sakai , Munetoshi Irisawa , Toyokazu Komuro , Yasuo Kaneda , Masanori Natsuka , Wakana Aizawa
IPC分类号： H01L23/12 , H01L21/00
CPC分类号： H05K3/064 , H05K1/116 , H05K3/0094 , H05K3/061 , H05K3/065 , H05K3/108 , H05K3/421 , H05K3/427 , H05K2201/09381 , H05K2201/09563 , H05K2201/09581 , H05K2201/098 , H05K2203/0517 , H05K2203/0577 , H05K2203/0582 , H05K2203/1184 , H05K2203/1394
摘要： As means for solving a problem of a positional shift of a land and a hole which is caused by an alignment in the formation of an etching resist layer and a plated resist layer in a method of manufacturing a circuit board, there are provided a method of manufacturing a circuit board including the steps of forming a first resin layer on a surface of an insulating substrate having a conductive layer on the surface and an internal wall of a through hole or/and a non-through hole, forming a second resin layer which is insoluble or slightly soluble in a developing solution for the first resin layer on the first resin layer provided on the surface conductive layer, and removing the first resin layer provided over the hole with the developing solution for the first resin layer, and a method of manufacturing a circuit board including the step of uniformly charging a surface of the first resin layer to induce a potential difference to the first resin layer provided over the hole and the first resin layer provided on the surface conductive layer before forming the second resin layer. Moreover, there is provided a circuit board having a hole with a small positional shift and high precision.
摘要翻译：作为在电路基板的制造方法中解决在形成抗蚀剂层和电镀抗蚀剂层时的取向引起的焊盘和孔的位置偏移的问题的方法，提供了一种方法，制造电路板，包括以下步骤：在表面上具有导电层的绝缘基板的表面上形成第一树脂层和通孔或/或非通孔的内壁，形成第二树脂层，所述第二树脂层在设置在表面导电层上的第一树脂层上的第一树脂层的显影液中不溶或微溶，用第一树脂层的显影液除去设在孔上的第一树脂层，制造电路板，包括对第一树脂层的表面均匀充电以对设置在孔上的第一树脂层引起电位差的步骤，在形成第二树脂层之前，在表面导电层上设置阴极层。此外，提供一种电路板，其具有位置偏移小且精度高的孔。

10. 发明授权

US07005241B2 Process for making circuit board or lead frame 失效
标题翻译：制造电路板或引线框架的工艺
公开(公告)号：US07005241B2
公开(公告)日：2006-02-28
申请号：US10822825
申请日：2004-04-13
申请人： Katsuya Fukase , Toyoaki Sakai
发明人： Katsuya Fukase , Toyoaki Sakai
IPC分类号： G03F7/00
CPC分类号： G03F7/0035 , H01L21/4828 , H01L21/4846 , H05K3/062 , H05K3/064 , H05K3/202 , H05K2203/0369 , H05K2203/0508 , H05K2203/058 , H05K2203/0597 , H05K2203/1476
摘要： A process for making a circuit board comprises the following steps of: half-etching a metal layer formed on an insulating substrate by means of a first masking which is positioned on an upper surface of the metal layer; applying a positive liquid resist on the half-etched metal layer from an upper side of the first masking; exposing the positive liquid resist with parallel light from the upper side of the first masking and developing the positive liquid resist in such a manner that a part of the positive liquid resist located under the first masking is protected to be unexposed and undeveloped; etching again the metal layer by means of a second masking composed of the first masking and the protected positive liquid resist to form a conductive pattern on the insulating substrate; and removing the first masking and the second masking from the metal layer.
摘要翻译：制造电路板的方法包括以下步骤：通过位于金属层的上表面上的第一掩模半蚀刻在绝缘基板上形成的金属层; 从第一掩模的上侧在半蚀刻金属层上施加正的液体抗蚀剂; 以平行的光从第一掩模的上侧露出正的液体抗蚀剂，并以这样的方式显影出正的液体抗蚀剂，使得位于第一掩蔽下的正极抗蚀剂的一部分被保护为未曝光和未显影; 通过由第一掩模和受保护的正性液体抗蚀剂构成的第二掩模再次蚀刻金属层，以在绝缘基板上形成导电图案; 以及从金属层去除第一掩蔽和第二掩蔽。

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