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1. 发明授权

US06784539B2 Thermally enhanced semiconductor chip having integrated bonds over active circuits 有权
公开(公告)号：US06784539B2
公开(公告)日：2004-08-31
申请号：US10603711
申请日：2003-06-25
申请人： Taylor R. Efland
发明人： Taylor R. Efland
IPC分类号： H01L2334
CPC分类号： H01L24/05 , H01L23/367 , H01L23/3677 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/0401 , H01L2224/04042 , H01L2224/05553 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/16 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45164 , H01L2224/45169 , H01L2224/48011 , H01L2224/4809 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48639 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/48739 , H01L2224/48764 , H01L2224/48769 , H01L2224/48839 , H01L2224/48844 , H01L2224/48864 , H01L2224/49111 , H01L2224/49174 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01083 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/20752 , H01L2924/30107 , H01L2924/351 , H01L2924/00014 , H01L2924/20658 , H01L2924/00 , H01L2924/00012 , H01L2224/05556 , H01L2224/48869 , H01L2224/48744 , H01L2924/0002 , H01L2924/20753
摘要： An integrated circuit (IC) chip has a metal network of electrical power distribution lines which have a thermal conductance at least an order of magnitude greater than underlying thin film electrical interconnects. These lines are deposited on the surface of the chip (FIG. 2), located directly over active IC components, and electrically and thermally connected vertically to selected active components below the lines. Electrical conductors are operable to connect the lines to an outside source, and additional electrically non-functional conductors are distributed on the lines, operable to steepen the thermal gradient for thermal flux away from said active components and lines.

2. 发明授权

US06729886B2 Method of fabricating a drain isolated LDMOS device 有权
标题翻译：制造漏极隔离LDMOS器件的方法
公开(公告)号：US06729886B2
公开(公告)日：2004-05-04
申请号：US10167283
申请日：2002-06-11
申请人： Taylor R. Efland , Chin-Yu Tsai
发明人： Taylor R. Efland , Chin-Yu Tsai
IPC分类号： H01L218238
CPC分类号： H01L21/761 , H01L29/1083 , H01L29/7835
摘要： A tank-isolated drain extended power device (50, 60, 70, 80) having an added laterally extending heavily doped p-type region (56, 62, 72) in combination with a p-type Dwell (32) which reduces minority carrier buildup. The p-doped regions are defined in a P-epi layer surrounded by a buried NBL region (14) connected with a deep low resistance drain region (16) forming a guardring. This additional laterally extending p-doped region (56,62,72) reduces minority carrier build up such that recovery time is significantly reduced, and power loss is also significantly reduced due to reduced collection time of the minority carriers. The device may be formed as an LDMOS device.
摘要翻译：一个槽隔离漏极扩展功率器件（50,60,70,80），其具有与p型Dwell（32）组合的附加横向延伸的重掺杂p型区域（56,62,72），其减少少数载流子积聚。 p掺杂区域限定在由与形成防护层的深低电阻漏极区域（16）连接的掩埋NBL区域（14）围绕的P外延层中。这种额外的横向延伸的p掺杂区域（56,62,72）减少了少数载流子的积累，使得恢复时间显着降低，并且由于少数载流子的收集时间减少，功率损耗也显着降低。该器件可以形成为LDMOS器件。

3. 发明授权

US06709900B2 Method of fabricating integrated system on a chip protection circuit 有权
标题翻译：在芯片保护电路上制造集成系统的方法
公开(公告)号：US06709900B2
公开(公告)日：2004-03-23
申请号：US10166964
申请日：2002-06-11
申请人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Dale Skelton , David D. Briggs , Chin-Yu Tsai
发明人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Dale Skelton , David D. Briggs , Chin-Yu Tsai
IPC分类号： H01L21332
CPC分类号： H01L29/1083 , H01L21/761 , H01L21/765 , H01L29/1045 , H01L29/7835
摘要： A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.
摘要翻译：一种功率集成电路架构（10），其具有插入在控制电路（152）和低侧晶体管（100）之间的高侧晶体管（100），以降低所述低侧晶体管对所述控制电路的操作的影响。低侧晶体管具有高p掺杂区域（56），其被设计为减少少数载流子寿命并改善少数载流子收集以减少少数载流子扰乱控制电路。低侧晶体管具有被连接到模拟地的保护（16），由此将控制电路连接到数字地，使得将少数载流子收集到模拟地中不会干扰控制电路的操作。低侧晶体管包括由至少一个深n型区域（16）分隔的多个晶体管阵列（90），该深n型区域围绕相应的晶体管阵列形成保护。防护器将一个晶体管阵列中的少数载流子与另一晶体管阵列隔离，并且便于通过其中的少数载流子的收集。

4. 发明授权

US06680226B2 Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology 有权
标题翻译：在深亚微米技术中优化数字和模拟CMOS晶体管性能的方法和设备
公开(公告)号：US06680226B2
公开(公告)日：2004-01-20
申请号：US10230559
申请日：2002-08-29
申请人： Taylor R. Efland , Alec J. Morton , Chin-Yu Tsai
发明人： Taylor R. Efland , Alec J. Morton , Chin-Yu Tsai
IPC分类号： H01L218238
CPC分类号： H01L21/823412 , H01L27/088
摘要： High performance digital transistors (140) and analog transistors (144, 146) are formed at the same time. The digital transistors (140) include first pocket regions (134) for optimum performance. These pocket regions (134) are masked from at least the drain side of the analog transistors (144, 146) to provide a flat channel doping profile on the drain side. Second pocket regions (200) may be formed in the analog transistors. The flat channel doping profile provides high early voltage and higher gain.
摘要翻译：高性能数字晶体管（140）和模拟晶体管（144,146）同时形成。数字晶体管（140）包括用于最佳性能的第一口袋区域（134）。从模拟晶体管（144,146）的至少漏极侧对这些凹区（134）进行掩模，以在漏极侧提供平坦的沟道掺杂分布。第二袋区（200）可以形成在模拟晶体管中。平坦沟道掺杂分布提供高的早期电压和更高的增益。

5. 发明授权

US06483149B1 LDMOS device with self-aligned resurf region and method of fabrication 失效
标题翻译：具有自对准复制区域的LDMOS器件和制造方法
公开(公告)号：US06483149B1
公开(公告)日：2002-11-19
申请号：US08856498
申请日：1997-05-14
申请人： Dan M. Mosher , Taylor R. Efland
发明人： Dan M. Mosher , Taylor R. Efland
IPC分类号： H01L27092
CPC分类号： H01L29/7835 , H01L29/1045 , H01L29/42368 , H01L29/66659
摘要： A RESURF LDMOS transistor (64) includes a RESURF region (42) that is self-aligned to a LOCOS field oxide region (44). The self-alignment produces a stable breakdown voltage BVdss by eliminating degradation associated with geometric misalignment and process tolerance variation.
摘要翻译： RESURF LDMOS晶体管（64）包括与LOCOS场氧化物区域（44）自对准的RESURF区域（42）。自对准通过消除与几何不对准和工艺公差变化相关的劣化产生稳定的击穿电压BVdss。

6. 发明授权

US6160290A Reduced surface field device having an extended field plate and method for forming the same 有权
公开(公告)号：US6160290A
公开(公告)日：2000-12-12
申请号：US196879
申请日：1998-11-20
申请人： Sameer P. Pendharkar , Taylor R. Efland
发明人： Sameer P. Pendharkar , Taylor R. Efland
IPC分类号： H01L29/06 , H01L29/40 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/7835 , H01L29/402 , H01L29/7813
摘要： A semiconductor device (10) comprises a reduced surface field (RESURF) implant (14). A field oxide layer (20), having a length, is formed over the RESURF implant (14). A field plate (12) extends from a near-side of the field oxide layer (20) and over at least one-half of the length of the field oxide layer (20).

7. 发明授权

US6150722A Ldmos transistor with thick copper interconnect 失效
标题翻译： Ldmos晶体管采用厚铜互连
公开(公告)号：US6150722A
公开(公告)日：2000-11-21
申请号：US538873
申请日：1995-10-04
申请人： Taylor R. Efland , Dave Cotton , Dale J. Skelton
发明人： Taylor R. Efland , Dave Cotton , Dale J. Skelton
IPC分类号： H01L29/43 , H01L21/28 , H01L23/482 , H01L23/528 , H01L23/532 , H01L29/06 , H01L29/417 , H01L29/45 , H01L29/78 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/7835 , H01L23/4824 , H01L23/5286 , H01L29/41758 , H01L29/7801 , H01L23/53228 , H01L29/0696 , H01L29/41775 , H01L29/456 , H01L2924/0002
摘要： A thick copper interconnection structure and method for an LDMOS transistor for power semiconductor devices. A large LDMOS transistor is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain. Gate regions are formed between the alternating source and drain diffusions. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form a source and a drain bus. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive copper layer. The thick third level metal bus substantially lowers the resistance of the LDMOS transistor and further eliminates current debiasing and early failure location problems experienced with LDMOS transistors of the prior art. Other devices and methods are described.
摘要翻译：一种用于功率半导体器件的LDMOS晶体管的厚铜互连结构和方法。大的LDMOS晶体管由多个源极和漏极扩散区域形成以耦合在一起以形成源极和漏极。栅极区域形成在交替的源极和漏极扩散之间。每个扩散区具有形成在其上并与其电接触的第一金属层条纹。第二金属层导体形成在多个第一金属层条纹上，并且选择性地接触第一金属层条纹以形成源极和漏极总线。然后在每个第二金属层母线上形成厚的第三金属层，或者物理地接触它或选择性地电接触它。厚三层金属由高导电铜层制成。厚的第三级金属总线大大降低了LDMOS晶体管的电阻，并进一步消除了现有技术的LDMOS晶体管所经历的电流去差和早期故障定位问题。描述其他设备和方法。

8. 发明授权

US5869882A Zener diode structure with high reverse breakdown voltage 失效
标题翻译：具有高反向击穿电压的齐纳二极管结构
公开(公告)号：US5869882A
公开(公告)日：1999-02-09
申请号：US724575
申请日：1996-09-30
申请人： Wayne T. Chen , Ross E. Teggatz , Taylor R. Efland
发明人： Wayne T. Chen , Ross E. Teggatz , Taylor R. Efland
IPC分类号： H01L29/866 , H01L29/861 , H01L31/107
CPC分类号： H01L29/866 , H01L29/0692 , H01L29/402 , H01L29/66106
摘要： A zener diode capable of breakdown at much higher voltages than in the prior art is fabricated by providing a semiconductor substrate of a first conductivity type having an opposite conductivity type first tank disposed therein. The first tank includes relatively lower and relatively higher resistivity portions, the relatively lower doped portion isolating the relatively higher doped portion from the substrate. A first region of first conductivity type is disposed in the higher doped portion and a second region of opposite conductivity type and more highly doped than the first tank is spaced from the first region. Structure is provided between the first and second regions for repelling majority charge carriers associated with the opposite conductivity type which can be a field plate spaced from the first tank; a portion at the surface of the first tank having the first conductivity type; or a tank, of first conductivity type disposed in the first tank, abutting the first region, extending more deeply into the first tank than does the first region and more lightly doped than the first region. In accordance with a further embodiment, the diode includes a semiconductor substrate, a first tank portion disposed in the substrate and a second tank portion disposed in the first tank portion as in the prior embodiments. A first region of first conductivity type is disposed in the second tank portion and extends into the first tank portion. A second region of opposite conductivity type more highly doped than the first tank portion is disposed in the first tank portion and spaced from the first region.
摘要翻译：能够以比现有技术高得多的电压击穿的齐纳二极管通过提供具有设置在其中的具有相反导电类型的第一容器的第一导电类型的半导体衬底来制造。第一罐包括相对较低和相对较高的电阻率部分，相对较低的掺杂部分将相对较高的掺杂部分与衬底隔离。第一导电类型的第一区域设置在较高掺杂部分中，并且具有相反导电类型的第二区域和比第一容器更高掺杂的第二区域与第一区域间隔开。在第一和第二区域之间提供结构，用于排斥与相反导电类型相关联的多数电荷载体，其可以是与第一罐间隔开的场板; 第一罐的表面上具有第一导电类型的部分; 或第一导电类型的罐，邻接第一区域，比第一区域更深地延伸到第一槽中，并且比第一区域更轻地掺杂。根据另一实施例，二极管包括半导体衬底，设置在衬底中的第一容器部分和如先前实施例中那样设置在第一容器部分中的第二容器部分。第一导电类型的第一区域设置在第二罐部分中并延伸到第一罐部分中。与第一容器部分相比更高掺杂的相反导电类型的第二区域设置在第一罐部分中并与第一区域间隔开。

9. 发明授权

US5406110A Resurf lateral double diffused insulated gate field effect transistor 失效
标题翻译：横向双扩散绝缘栅场效应晶体管
公开(公告)号：US5406110A
公开(公告)日：1995-04-11
申请号：US191228
申请日：1994-02-01
申请人： Oh-Kyong Kwon , Taylor R. Efland , Satwinder Malhi , Wai T. Ng
发明人： Oh-Kyong Kwon , Taylor R. Efland , Satwinder Malhi , Wai T. Ng
IPC分类号： H01L29/08 , H01L29/78 , H01L27/092 , H01L27/105
CPC分类号： H01L29/66681 , H01L29/7801 , H01L29/7816 , H01L29/7835 , H01L29/0847 , H01L29/0878 , Y10S148/096
摘要： A transistor (10) has a thin epitaxial layer (14) of a second conductivity type on a semiconductor substrate (12) of a first conductivity type. A drift region (24) of the second conductivity type is formed extending through the thin epitaxial layer (14) to the substrate (12). A thick insulator layer (26) is formed on the drift region (24). An IGFET body (28) of the first conductivity type is formed adjacent the drift region (24). A source region (34) of the second conductivity type is formed within the IGFET body (28) and spaced from the drift region (24) defining a channel region (40) within the IGFET body (28). A conductive gate (32) is insulatively disposed over the IGFET body (28) and extends from the source region (34) to the thick insulator layer (26). A drain region (36) is formed adjacent the drift region (24).
摘要翻译：晶体管（10）在第一导电类型的半导体衬底（12）上具有第二导电类型的薄外延层（14）。形成第二导电类型的漂移区（24），延伸穿过薄外延层（14）到衬底（12）。在漂移区（24）上形成厚的绝缘体层（26）。第一导电类型的IGFET体（28）形成在漂移区（24）附近。第二导电类型的源极区域（34）形成在IGFET主体（28）内并且与漂移区域（24）间隔开，从而限定IGFET体（28）内的沟道区域（40）。导电栅极（32）被绝缘地设置在IGFET主体（28）上并且从源极区域（34）延伸到厚的绝缘体层（26）。在漂移区（24）附近形成漏区（36）。

10. 发明授权

US5182222A Process for manufacturing a DMOS transistor 失效
标题翻译：制造DMOS晶体管的工艺
公开(公告)号：US5182222A
公开(公告)日：1993-01-26
申请号：US720570
申请日：1991-06-26
申请人： Satwinder Malhi , Taylor R. Efland
发明人： Satwinder Malhi , Taylor R. Efland
IPC分类号： H01L21/265 , H01L21/336 , H01L29/10 , H01L29/78
CPC分类号： H01L29/66712 , H01L29/1095 , H01L29/7802 , Y10S148/126
摘要： A method is provided for manufacturing a semiconductor device at a face of a semiconductor layer having a first conductivity type. Over the semiconductor layer and insulating therefrom a gate conductive layer is formed, which has a predetermined pattern defining an opening. A well of a second conductivity type is then implanted into the face of the semiconductor layer by self-aligning to the sidewall of the gate conductive layer. A first surface region of the first conductivity type is formed within the well and self-aligned to the sidewall of the gate conductive layer. A sacrificial sidewall layer is formed in the opening which defines a second narrower opening, so that a subsurface region of the second conductivity type may be formed within the well self-aligned to the sacrificial sidewall layer. A second surface region of the second conductivity type is then formed substantially within the first surface region and self-aligned to the sacrificial sidewall layer. The construct of the first and second surface regions is such that the second surface region at the face of the semiconductor layer is substantially surrounded by the first surface region. The sacrificial sidewall layer is removed and a thinner insulating sidewall is formed in the opening. In this manner, the second surface region as well as a portion of the first surface region substantially surrounding the first surface region are exposed. Subsequently, a source electrode contacting the exposed second surface region and the exposed first surface region substantially surrounding the second surface region at the face of said semiconductor layer is formed.
摘要翻译：提供了在具有第一导电类型的半导体层的表面上制造半导体器件的方法。在半导体层上并与其绝缘，形成具有限定开口的预定图案的栅极导电层。然后通过与栅极导电层的侧壁自对准将第二导电类型的阱注入到半导体层的表面中。第一导电类型的第一表面区域形成在阱内并与栅极导电层的侧壁自对准。牺牲侧壁层形成在开口中，其限定第二较窄的开口，使得可以在与牺牲侧壁层自对准的阱内形成第二导电类型的次表面区域。然后第二导电类型的第二表面区域基本上形成在第一表面区域内并且与牺牲侧壁层自对准。第一表面区域和第二表面区域的构造使得半导体层的表面处的第二表面区域被第一表面区域基本包围。牺牲侧壁层被去除，并且在开口中形成更薄的绝缘侧壁。以这种方式，露出第二表面区域以及基本上围绕第一表面区域的第一表面区域的一部分。随后，形成与所述暴露的第二表面区域接触的源电极和基本上围绕所述半导体层的表面处的第二表面区域的暴露的第一表面区域。

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