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1. 发明授权

US06380068B2 Method for planarizing a flash memory device 有权
标题翻译：闪存器件的平面化方法
公开(公告)号：US06380068B2
公开(公告)日：2002-04-30
申请号：US09783459
申请日：2001-02-14
申请人： Pei-Ren Jeng , Shu Li Wu
发明人： Pei-Ren Jeng , Shu Li Wu
IPC分类号： H01L214763
CPC分类号： H01L21/31056
摘要： A method to planarize a flash memory device, wherein the method is applied on a substrate having a polysilicon layer and a cap layer sequentially formed thereon. Thereafter, the cap layer and the polysilicon layer are patterned to form the peripheral circuit region and the memory cell region. A dielectric layer is then formed on the substrate, covering the cap layer. A portion of the dielectric layer is further removed to expose a part of the cap layer, such that the dielectric layer above the cap layer and the dielectric layer on both sides of the cap layer become separated. A portion of the dielectric layer in the peripheral circuit region is then removed, followed by removing the cap layer, wherein the dielectric layer above the cap layer is concurrently removed to complete the planazation of the flash memory device.
摘要翻译：一种平面化闪速存储器件的方法，其中所述方法被施加在其上顺序地形成有多晶硅层和盖层的衬底上。此后，盖层和多晶硅层被图案化以形成外围电路区域和存储单元区域。然后在衬底上形成介电层，覆盖覆盖层。进一步去除电介质层的一部分以露出盖层的一部分，使得覆盖层上方的电介质层和盖层两侧的电介质层变得分离。然后去除外围电路区域中的介电层的一部分，随后去除覆盖层，其中同时去除覆盖层上方的电介质层以完成闪存器件的平面化。

2. 发明授权

US06706596B2 Method for forming flash memory cell 有权
标题翻译：形成闪存单元的方法
公开(公告)号：US06706596B2
公开(公告)日：2004-03-16
申请号：US10209855
申请日：2002-08-02
申请人： Ping-Yi Chang , Wan-Yi Liu , Shu-Li Wu
发明人： Ping-Yi Chang , Wan-Yi Liu , Shu-Li Wu
IPC分类号： H01L218247
CPC分类号： H01L27/115 , H01L27/11521
摘要： The present invention provides a method for forming a flash memory cell and comprises following steps. First, a substrate is provided. Then, a gate dielectric layer, a first polysilicon layer and a hard mask layer are sequentially formed on the substrate. Next, a portion of the hard mask layer, the polysilicon layer, and the gate dielectric layer are removed to form a plurality of holes to expose the substrate. Following, a dielectric layer is formed in those holes by a HDPCVD process. Last, the hard mask layer on the first polysilicon layer is removed by the HDPCVD process. Further, a second polysilicon layer could be conformally formed on the first polysilicon layer and the isolation dielectric.
摘要翻译：本发明提供一种形成闪存单元的方法，包括以下步骤。首先，提供基板。然后，在衬底上依次形成栅介电层，第一多晶硅层和硬掩模层。接下来，去除硬掩模层，多晶硅层和栅极电介质层的一部分以形成多个孔以露出衬底。接下来，通过HDPCVD工艺在这些孔中形成介电层。最后，通过HDPCVD工艺去除第一多晶硅层上的硬掩模层。此外，第二多晶硅层可以共形地形成在第一多晶硅层和隔离电介质上。

3. 发明授权

US06335274B1 Method for forming a high-RI oxide film to reduce fluorine diffusion in HDP FSG process 有权
标题翻译：用于形成高RI氧化膜以减少HDP FSG工艺中的氟扩散的方法
公开(公告)号：US06335274B1
公开(公告)日：2002-01-01
申请号：US09714128
申请日：2000-11-17
申请人： Shu-Li Wu , Pei-Ren Jeng
发明人： Shu-Li Wu , Pei-Ren Jeng
IPC分类号： H01L214763
CPC分类号： H01L21/02131 , H01L21/02304 , H01L21/31612 , H01L21/31629 , H01L21/76834
摘要： A method for forming a high-RI dielectric liner layer to prevent out diffusion of fluorine substances in an intermetal dielectric (IMD) layer of an semiconductor device is provided. The method comprises following steps. First, a patterned conductive layer is deposited on a substrate. Then, a dielectric liner layer is formed by high density plasma enhanced chemical vapor deposition method or plasma enhanced chemical vapor deposition method. The dielectric liner layer is silicon dioxide and has a high-RI between about 1.5 to 1.8. Next, a fluorinated silicate glass layer is deposited on the dielectric liner layer. The high-RI dielectric liner layer is used to reduce out diffusion of fluorine substances in the fluorinated silicate glass layer. Last, it is proceeded a chemical mechanism polishing process to remove additional fluorinated silicate glass layer and the dielectric liner layer.
摘要翻译：提供了形成高RI电介质衬垫层以防止氟物质在半导体器件的金属间电介质（IMD）层中的扩散的方法。该方法包括以下步骤。首先，将图案化的导电层沉积在衬底上。然后，通过高密度等离子体增强化学气相沉积法或等离子体增强化学气相沉积法形成电介质衬垫层。电介质衬垫层是二氧化硅，并且具有在约1.5至1.8之间的高RI。接下来，氟化硅酸盐玻璃层沉积在电介质衬垫层上。高RI介电衬垫层用于减少氟化硅酸盐玻璃层中氟物质的扩散。最后，进行化学机构抛光工艺以除去附加的氟化硅酸盐玻璃层和介电衬里层。

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