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1. 发明申请

US20090176346A1 Monitor pattern of semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体器件的监视器模式及制造半导体器件的方法
公开(公告)号：US20090176346A1
公开(公告)日：2009-07-09
申请号：US12379967
申请日：2009-03-05
申请人： Sachie Tone , Hiroyuki Uno , Naoki Tanahashi , Naoki Nishida
发明人： Sachie Tone , Hiroyuki Uno , Naoki Tanahashi , Naoki Nishida
IPC分类号： H01L21/70 , H01L23/58
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.
摘要翻译：多个扩散电阻器和多个布线（电阻元件）沿虚拟线交替布置，并且这些扩散电阻器和布线通过接触通孔串联连接。在与布线的布线层相同的布线层中，形成虚线图案以围绕布线的形成区域和扩散电阻器。虚设图案和布线之间的空间根据例如芯片形成部分中的布线之间的最小间隔来设定。

2. 发明授权

US07883982B2 Monitor pattern of semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体器件的监视器模式及制造半导体器件的方法
公开(公告)号：US07883982B2
公开(公告)日：2011-02-08
申请号：US12379967
申请日：2009-03-05
申请人： Sachie Tone , Hiroyuki Uno , Naoki Tanahashi , Naoki Nishida
发明人： Sachie Tone , Hiroyuki Uno , Naoki Tanahashi , Naoki Nishida
IPC分类号： H01L21/20
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.
摘要翻译：多个扩散电阻器和多个布线（电阻元件）沿虚拟线交替布置，并且这些扩散电阻器和布线通过接触通孔串联连接。在与布线的布线层相同的布线层中，形成虚线图案以围绕布线的形成区域和扩散电阻器。虚设图案和布线之间的空间根据例如芯片形成部分中的布线之间的最小间隔来设定。

3. 发明申请

US20060081842A1 Monitor pattern of semiconductor device and method of manufacturing semiconductor device 审中-公开
公开(公告)号：US20060081842A1
公开(公告)日：2006-04-20
申请号：US11273294
申请日：2005-11-15
申请人： Sachie Tone , Hiroyuki Uno , Naoki Tanahashi , Naoki Nishida
发明人： Sachie Tone , Hiroyuki Uno , Naoki Tanahashi , Naoki Nishida
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.

4. 发明授权

US07301169B2 Semiconductor substrate and semiconductor device fabrication method 有权
标题翻译：半导体衬底和半导体器件制造方法
公开(公告)号：US07301169B2
公开(公告)日：2007-11-27
申请号：US10995539
申请日：2004-11-24
申请人： Sachie Tone , Hiroshi Ohta , Masahiro Ninomiya
发明人： Sachie Tone , Hiroshi Ohta , Masahiro Ninomiya
IPC分类号： H01L23/58
CPC分类号： H01L21/6836 , H01L23/544 , H01L24/05 , H01L2221/68327 , H01L2221/6834 , H01L2221/68386 , H01L2223/54453 , H01L2224/02166 , H01L2224/05554 , H01L2224/05556
摘要： The semiconductor substrate comprises a first monitor part 14a formed in a first region near a center of a semiconductor wafer 10, which includes a first element having a first electrode 24 formed over the semiconductor wafer 10 with a first insulation film 22 formed therebetween, and a first electrode pad 32 electrically connected to the first electrode 24; and a second monitor part 14b formed in a second region different from the first region, which includes a second element having a second electrode 24 formed on the semiconductor wafer 10 with a second insulation film 22 formed therebetween, and a second electrode pad 32 electrically connected to the second electrode 24. When electric breakdown has taken place in both the first monitor part 14a and the second monitor part 14b, it can be judged that too large static electricity was generated upon the release of the surface protection film 39. When electric breakdown has taken place in either of the first monitor part 14a and the second monitor part 14b, the electric breakdown has taken place due to factors other than the static electricity generated upon the release of the surface protection film. When electric breakdown has taken place in neither of the first monitor part 14a and the second monitor part 14b, it can be judged that too large static electricity was generated upon the release of the surface protection film 39. Thus, factors for defects of semiconductor devices can be identified, which leads to improved quality of the semiconductor devices.
摘要翻译：半导体衬底包括形成在半导体晶片10的中心附近的第一区域中的第一监视器部分14a，其包括第一元件，第一元件具有形成在半导体晶片10上的第一电极24，其间形成有第一绝缘膜22;以及电连接到第一电极24的第一电极焊盘32; 以及形成在与第一区域不同的第二区域中的第二监视器部分14b，其包括第二元件，第二元件具有形成在半导体晶片10上的第二电极24，其间形成有第二绝缘膜22，第二电极焊盘32电连接连接到第二电极24。当在第一监视器部分14a和第二监视器部分14b两者中发生电击穿时，可以判断出在释放表面保护膜39时产生太大的静电。当在第一监视器部分14a和第二监视器部分14b中的任一个中发生电击穿时，由于除了表面保护膜释放后产生的静电以外的因素而发生电击穿。当在第一监视器部分14a和第二监视器部分14b中都没有发生电击穿时，可以判断出在释放表面保护膜39时产生太大的静电。因此，可以识别半导体器件缺陷的因素，这导致半导体器件的质量提高。

5. 发明授权

US06992327B2 Monitor pattern of semiconductor device and method of manufacturing semiconductor device 有权
公开(公告)号：US06992327B2
公开(公告)日：2006-01-31
申请号：US10447956
申请日：2003-05-30
申请人： Sachie Tone , Hiroyuki Uno , Naoki Tanahashi , Naoki Nishida
发明人： Sachie Tone , Hiroyuki Uno , Naoki Tanahashi , Naoki Nishida
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.

6. 发明授权

US08298903B2 Monitor pattern of semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体器件的监视器模式及制造半导体器件的方法
公开(公告)号：US08298903B2
公开(公告)日：2012-10-30
申请号：US12974462
申请日：2010-12-21
申请人： Sachie Tone , Hiroyuki Uno , Naoki Takahashi , Naoki Nishida
发明人： Sachie Tone , Hiroyuki Uno , Naoki Takahashi , Naoki Nishida
IPC分类号： H01L21/20
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.
摘要翻译：多个扩散电阻器和多个布线（电阻元件）沿虚拟线交替布置，并且这些扩散电阻器和布线通过接触通孔串联连接。在与布线的布线层相同的布线层中，形成虚线图案以围绕布线的形成区域和扩散电阻器。虚设图案和布线之间的空间根据例如芯片形成部分中的布线之间的最小间隔来设定。

7. 发明申请

US20110092042A1 MONITOR PATTERN OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的显示器图案及制造半导体器件的方法
公开(公告)号：US20110092042A1
公开(公告)日：2011-04-21
申请号：US12974462
申请日：2010-12-21
申请人： Sachie TONE , Hiroyuki UNO , Naoki TANAHASHI , Naoki NISHIDA
发明人： Sachie TONE , Hiroyuki UNO , Naoki TANAHASHI , Naoki NISHIDA
IPC分类号： H01L21/02
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.
摘要翻译：多个扩散电阻器和多个布线（电阻元件）沿虚拟线交替布置，并且这些扩散电阻器和布线通过接触通孔串联连接。在与布线的布线层相同的布线层中，形成虚线图案以围绕布线的形成区域和扩散电阻器。虚设图案和布线之间的空间根据例如芯片形成部分中的布线之间的最小间隔来设定。

8. 发明申请

US20060022196A1 Semiconductor substrate and semiconductor device fabrication method 有权
标题翻译：半导体衬底和半导体器件制造方法
公开(公告)号：US20060022196A1
公开(公告)日：2006-02-02
申请号：US10995539
申请日：2004-11-24
申请人： Sachie Tone , Hiroshi Ohta , Masahiro Ninomiya
发明人： Sachie Tone , Hiroshi Ohta , Masahiro Ninomiya
IPC分类号： H01L23/58 , H01L29/10
CPC分类号： H01L21/6836 , H01L23/544 , H01L24/05 , H01L2221/68327 , H01L2221/6834 , H01L2221/68386 , H01L2223/54453 , H01L2224/02166 , H01L2224/05554 , H01L2224/05556
摘要： The semiconductor substrate comprises a first monitor part 14a formed in a first region near a center of a semiconductor wafer 10, which includes a first element having a first electrode 24 formed over the semiconductor wafer 10 with a first insulation film 22 formed therebetween, and a first electrode pad 32 electrically connected to the first electrode 24; and a second monitor part 14b formed in a second region different from the first region, which includes a second element having a second electrode 24 formed on the semiconductor wafer 10 with a second insulation film 22 formed therebetween, and a second electrode pad 32 electrically connected to the second electrode 24. When electric breakdown has taken place in both the first monitor part 14a and the second monitor part 14b, it can be judged that too large static electricity was generated upon the release of the surface protection film 39. When electric breakdown has taken place in either of the first monitor part 14a and the second monitor part 14b, the electric breakdown has taken place due to factors other than the static electricity generated upon the release of the surface protection film. When electric breakdown has taken place in neither of the first monitor part 14a and the second monitor part 14b, it can be judged that too large static electricity was generated upon the release of the surface protection film 39. Thus, factors for defects of semiconductor devices can be identified, which leads to improved quality of the semiconductor devices.
摘要翻译：半导体衬底包括形成在半导体晶片10的中心附近的第一区域中的第一监视器部分14a，其包括第一元件，第一元件具有形成在半导体晶片10上的第一电极24，其间形成有第一绝缘膜22;以及电连接到第一电极24的第一电极焊盘32; 以及形成在与第一区域不同的第二区域中的第二监视器部分14b，其包括第二元件，第二元件具有形成在半导体晶片10上的第二电极24，其间形成有第二绝缘膜22，第二电极焊盘32电连接连接到第二电极24.当在第一监视器部分14a和第二监视器部分14b中都发生电击穿时，可以判断出在释放表面保护膜39时产生太大的静电。当在第一监视器部分14a和第二监视器部分14b中的任一个中发生电击穿时，由于除了表面保护膜释放后产生的静电以外的因素而发生电击穿。当在第一监视器部分14a和第二监视器部分14b中都没有发生电击穿时，可以判断出在释放表面保护膜39时产生太大的静电。因此，可以识别半导体器件，这导致半导体器件的质量提高。

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