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1. 发明授权

US08357971B2 Trench gate MOSFET and method of manufacturing the same 有权
标题翻译：沟槽栅MOSFET及其制造方法
公开(公告)号：US08357971B2
公开(公告)日：2013-01-22
申请号：US12739341
申请日：2008-10-22
申请人： Steven Thomas Peake , Philip Rutter , Christopher Martin Rogers , Miron Drobnis , Andrew Butler
发明人： Steven Thomas Peake , Philip Rutter , Christopher Martin Rogers , Miron Drobnis , Andrew Butler
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/2251 , H01L21/26586 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/66734
摘要： A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region (3) of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.
摘要翻译：沟槽栅极MOS场效应晶体管，其具有从紧邻沟槽侧壁的相同导电类型的沟道容纳区域（3）延伸的窄的轻掺杂区域。窄区域可以与沟槽中的下多晶硅屏蔽区域的顶部自对准，或者可以延伸沟槽的整个深度。窄区域有利地放宽制造公差，否则需要上部多晶硅沟槽栅极与体 - 漏接合部紧密对准。

2. 发明申请

US20120037980A1 EDGE TERMINATION REGION 有权
标题翻译：边缘终止区域
公开(公告)号：US20120037980A1
公开(公告)日：2012-02-16
申请号：US13210308
申请日：2011-08-15
申请人： Steven Thomas Peake , Philip Rutter
发明人： Steven Thomas Peake , Philip Rutter
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/4238 , H01L29/7811
摘要： An isolation region (14) is formed between an edge termination region (2) having deep trenches (20,34) and the central region (4). The isolation region includes gate fingers (18) extending from the edge gate trench regions (28) to the gate trenches (6) in the central region (4) to electrically connect the edge gate trench regions to the gate trenches (6) in the central region. The isolation region also includes isolation fingers (22,24) extending from the edge termination region (2) towards the central region (4) and gate between the gate fingers (18) for reducing the breakdown voltage with a RESURF effect.
摘要翻译：在具有深沟槽（20,34）的边缘终端区域（2）和中心区域（4）之间形成隔离区域（14）。隔离区域包括从边缘栅极沟槽区域（28）延伸到中心区域（4）中的栅极沟槽（6）的栅极指（18），以将栅极沟槽区域电连接到栅极沟槽（6）中央区域。隔离区域还包括从边缘终端区域（2）向中心区域（4）延伸的隔离指状物（22,24）以及栅极指状物（18）之间的栅极，用于以RESURF效应降低击穿电压。

3. 发明授权

US07205821B2 Driver for switching circuit and drive method 失效
标题翻译：驱动器用于开关电路和驱动方式
公开(公告)号：US07205821B2
公开(公告)日：2007-04-17
申请号：US10536247
申请日：2003-11-19
申请人： Philip Rutter
发明人： Philip Rutter
IPC分类号： H03K17/687
CPC分类号： H02M1/38 , H02M3/1588 , H03K17/04123 , H03K17/04206 , Y02B70/1466
摘要： A driver circuit includes monitoring circuitry (32, 34, 36) for monitoring the states of high and low side switches (6, 8). The driver circuit has an adjustable delay for turning on the transistors (6, 8). The delay is decreased when the monitoring circuit detects that a voltage corresponding to one transistor passes a predetermined voltage V1 before a voltage corresponding to the other transistor passes another predetermined point V2, and vice versa.
摘要翻译：驱动器电路包括用于监视高侧和低侧开关（6,8）的状态的监控电路（32,34,36）。驱动电路具有用于导通晶体管（6,8）的可调延迟。当监视电路检测到与一个晶体管相对应的电压在与另一晶体管相对应的电压通过另一个预定点V 2之前通过预定电压V 1时，延迟减小，反之亦然。

4. 发明授权

US08513733B2 Edge termination region of a semiconductor device 有权
标题翻译：半导体器件的边缘端接区域
公开(公告)号：US08513733B2
公开(公告)日：2013-08-20
申请号：US13210308
申请日：2011-08-15
申请人： Steven Thomas Peake , Philip Rutter
发明人： Steven Thomas Peake , Philip Rutter
IPC分类号： H01L27/108 , H01L29/66 , H01L21/336 , H01L21/331
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/4238 , H01L29/7811
摘要： An isolation region (14) is formed between an edge termination region (2) having deep trenches (20,34) and the central region (4). The isolation region includes gate fingers (18) extending from the edge gate trench regions (28) to the gate trenches (6) in the central region (4) to electrically connect the edge gate trench regions to the gate trenches (6) in the central region. The isolation region also includes isolation fingers (22,24) extending from the edge termination region (2) towards the central region (4) and gate between the gate fingers (18) for reducing the breakdown voltage with a RESURF effect.
摘要翻译：在具有深沟槽（20,34）的边缘终端区域（2）和中心区域（4）之间形成隔离区域（14）。隔离区域包括从边缘栅极沟槽区域（28）延伸到中心区域（4）中的栅极沟槽（6）的栅极指（18），以将栅极沟槽区域电连接到栅极沟槽（6）中央区域。隔离区域还包括从边缘终端区域（2）向中心区域（4）延伸的隔离指状物（22,24）以及栅极指状物（18）之间的栅极，用于以RESURF效应降低击穿电压。

5. 发明申请

US20120070983A1 SEMICONDUCTOR DEVICE WITH GATE TRENCH 有权
标题翻译：带门极化的半导体器件
公开(公告)号：US20120070983A1
公开(公告)日：2012-03-22
申请号：US13237878
申请日：2011-09-20
申请人： Philip Rutter , Christopher Martin Rogers
发明人： Philip Rutter , Christopher Martin Rogers
IPC分类号： H01L21/768
CPC分类号： H01L29/7813 , H01L29/42372 , H01L29/4941 , H01L29/66734 , H01L29/7811
摘要： A method of manufacturing a semiconductor device is presented. The device has: a gate terminal formed from polysilicon and covered by an insulation layer; and a plug extending through an insulation layer to provide an electrical connection to the gate trench. A metal layer is deposited to cover at least a portion of the insulation layer. The metal layer is then etched to remove the metal layer from above the plug.
摘要翻译：提出了制造半导体器件的方法。该器件具有：由多晶硅形成并被绝缘层覆盖的栅极端子; 以及延伸穿过绝缘层以提供到栅极沟槽的电连接的插塞。沉积金属层以覆盖绝缘层的至少一部分。然后蚀刻金属层以从塞子上方去除金属层。

6. 发明申请

US20060038545A1 Driver for swicthing circuit and drive method 失效
标题翻译：驱动电路和驱动方式
公开(公告)号：US20060038545A1
公开(公告)日：2006-02-23
申请号：US10536247
申请日：2003-11-19
申请人： Philip Rutter
发明人： Philip Rutter
IPC分类号： G05F1/40
CPC分类号： H02M1/38 , H02M3/1588 , H03K17/04123 , H03K17/04206 , Y02B70/1466
摘要： A driver circuit includes monitoring circuitry (32, 34, 36) for monitoring the states of high and low side switches (6, 8). The driver circuit has an adjustable delay for turning on the transistors (6, 8). The delay is decreased when the monitoring circuit detects that a voltage corresponding to one transistor passes a predetermined voltage V1 before a voltage corresponding to the other transistor passes another predetermined point V2, and vice versa.
摘要翻译：驱动器电路包括用于监视高侧和低侧开关（6,8）的状态的监控电路（32,34,36）。驱动电路具有用于导通晶体管（6,8）的可调延迟。当监视电路检测到与一个晶体管相对应的电压在与另一晶体管相对应的电压通过另一个预定点V 2之前通过预定电压V 1时，延迟减小，反之亦然。

7. 发明申请

US20050173758A1 Trench-gate semiconductor devices 有权
标题翻译：沟槽栅半导体器件
公开(公告)号：US20050173758A1
公开(公告)日：2005-08-11
申请号：US10515748
申请日：2003-05-21
申请人： Steven Peake , Philip Rutter , Raymond Grover
发明人： Steven Peake , Philip Rutter , Raymond Grover
IPC分类号： H01L21/336 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7813 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/16 , H01L29/407 , H01L29/4232 , H01L29/7397 , H01L29/7825 , H01L29/7828 , H01L2224/05599 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2224/49111 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01082 , H01L2924/12036 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/19041 , H01L2924/3025 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A trench-gate semiconductor device, for example a MOSFET or IGBT, includes a semiconductor body (20) having a drain region (4) comprising a drain drift region (4a) and a drain contact region (4b). An insulated field plate (24) is included in the trench (10) between the gate (8) and the drain contact region (4b), wherein the field plate (24) is for connection to a bias potential greater than the gate potential and near to the bulk breakdown voltage of the drain drift region (4a). The field plate (24) causes the potential drop across the drain drift region (4a) to be spread considerably more evenly, particularly at applied voltages greater than the bulk breakdown voltage, thereby substantially increasing the breakdown voltage of the device.
摘要翻译：沟槽栅半导体器件，例如MOSFET或IGBT，包括具有包括漏极漂移区（4a）和漏极接触区（4b）的漏极区（4）的半导体本体（20）。绝缘场板（24）包括在栅极（8）和漏极接触区域（4b）之间的沟槽（10）中，其中场板（24）用于连接到大于栅极电位的偏置电位并且接近漏极漂移区域（4a）的体积击穿电压。场板（24）导致穿过漏极漂移区域（4a）的电位降明显地更均匀地扩散，特别是在大于体击穿电压的施加电压下，从而显着增加了器件的击穿电压。

8. 发明授权

US07102337B2 Feedback circuit for power switching circuit 有权
标题翻译：电源开关电路反馈电路
公开(公告)号：US07102337B2
公开(公告)日：2006-09-05
申请号：US10536244
申请日：2003-11-19
申请人： Nicolas J. Wheeler , Philip Rutter
发明人： Nicolas J. Wheeler , Philip Rutter
IPC分类号： G05F1/618
CPC分类号： H02M3/1588 , Y02B70/1466
摘要： A power switching circuit has high and low side switches (6, 8). The load-side FET (8) has a main body part (30) and a sense FET part (32). The current sensing circuit (32) measured the low side current. A capacitance (56) couples the switch node (10) to a current signal node (52) to provide a combined signal on current output (58), the combined signal including the low side current and timing information.
摘要翻译：电源开关电路具有高低侧开关（6,8）。负载侧FET（8）具有主体部（30）和感测用FET部（32）。电流检测电路（32）测量低端电流。电容（56）将开关节点（10）耦合到电流信号节点（52），以提供电流输出（58）上的组合信号，该组合信号包括低端电流和定时信息。

9. 发明申请

US20050208722A1 Trench-gate semiconductor device and method of manufacturing 失效
标题翻译：沟槽栅极半导体器件及其制造方法
公开(公告)号：US20050208722A1
公开(公告)日：2005-09-22
申请号：US10515749
申请日：2003-05-21
申请人： Steven Peake , Philip Rutter
发明人： Steven Peake , Philip Rutter
IPC分类号： H01L29/41 , H01L21/336 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/402 , H01L29/407 , H01L29/4232 , H01L29/4238 , H01L29/66674 , H01L29/7397 , H01L29/7801 , H01L29/7827 , H01L2224/05554 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2224/49111 , H01L2224/49171
摘要： A trench-gate semiconductor device, for example a MOSFET or IGBT, having a field plate (24) provided below the trenched gate (8) is manufactured using a process with improved reproducibility. The process includes the steps of etching a first grove (28a) into the semiconductor body (20) for receiving the gate (8), and etching a second groove (28b) into the top major surface (20a) of the semiconductor body (20), the second groove (28b) extending from the bottom of the first groove (28a) and being narrower than the first grove. The invention enables better control of the vertical extent of the gate below the top major surface (20a) of the semiconductor body.
摘要翻译：使用具有改进的再现性的工艺制造具有设置在沟槽栅极（8）下方的场板（24）的沟槽栅极半导体器件，例如MOSFET或IGBT。该方法包括以下步骤：将第一凹槽（28a）蚀刻到用于接收栅极（8）的半导体本体（20）中，并且将第二凹槽（28b）蚀刻到半导体的顶部主表面（20a）中主体（20），第二凹槽（28b）从第一凹槽（28a）的底部延伸并且比第一凹槽更窄。本发明能够更好地控制半导体主体的顶部主表面（20a）下方的栅极的垂直范围。

10. 发明授权

US06674268B2 Swithing regulator utilizing seperate integrated circuits for driving each switch 有权
标题翻译：开关稳压器采用单独的集成电路驱动每个开关
公开(公告)号：US06674268B2
公开(公告)日：2004-01-06
申请号：US10071396
申请日：2002-02-06
申请人： Philip Rutter , Leonardus A. De Groot , Nicolas J. Wheeler
发明人： Philip Rutter , Leonardus A. De Groot , Nicolas J. Wheeler
IPC分类号： G05F316
CPC分类号： H03K17/6871 , H02M1/08 , H02M1/38 , H02M3/1588 , H03K17/0822 , H03K17/165 , H03K2217/0036 , H03K2217/0081 , Y02B70/1466
摘要： A switching circuit for switching an input dc voltage of predetermined polarity is used, for example, for a synchronous dc-dc converter. The switching circuit is divided between a high side package (52) and a low side package (56) each having a logic input (90) and a switch (6,8) connected between switching outputs (84,86). The switching outputs (84,86) of the high and low side packages (52,56) are connected in series between input voltage terminals (4,2). A pulse width modulator (18) is connected to the logic inputs (90) of the packages for supplying an alternating control signal for switching the high and low side switches (6,8) alternately. Each of the high and low side packages (52,56) contains logic circuitry (150) for controlling the respective switch (6,8) based solely on the voltages on the respective logic input (90) and respective switching outputs (84,86) to prevent the switches (6,8) in the high and low side packages (52,56) from conducting at the same time. The logic circuitry (150) may use a predetermined delay or incorporate sense circuitry that switches based on the voltage on the outputs. In this way, the need for control interconnections between the high and low side packages (52,56) is avoided.
摘要翻译：用于切换预定极性的输入直流电压的开关电路例如用于同步dc-dc转换器。切换电路被分为高侧封装（52）和低侧封装（56），每个封装具有连接在开关输出（84,86）之间的逻辑输入（90）和开关（6,8）。高低侧封装（52,56）的开关输出（84,86）串联连接在输入电压端子（4,2）之间。脉冲宽度调制器（18）连接到封装的逻辑输入（90），用于提供用于交替切换高低侧开关（6,8）的交替控制信号。高和低侧封装（52,56）中的每一个包含逻辑电路（150），用于仅基于相应的逻辑输入（90）和相应的开关输出（84,86）上的电压来控制相应的开关（6,8））以防止高低侧封装（52,56）中的开关（6,8）同时导通。逻辑电路（150）可以使用预定的延迟或者包括基于输出上的电压来切换的感测电路。以这种方式，避免了在高低侧封装（52,56）之间的控制互连的需要。

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