专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08427865B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08427865B2
公开(公告)日：2013-04-23
申请号：US13440225
申请日：2012-04-05
申请人： Akio Shima , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
发明人： Akio Shima , Yoshitaka Sasago , Masaharu Kinoshita , Toshiyuki Mine , Norikatsu Takaura , Takahiro Morikawa , Kenzo Kurotsuchi , Satoru Hanzawa
IPC分类号： G11C11/00 , H01L29/80
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/003 , G11C2213/71 , G11C2213/75 , G11C2213/79 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1683
摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.
摘要翻译：提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以构成三维存储器单元格阵列。存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

2. 发明授权

US08129707B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08129707B2
公开(公告)日：2012-03-06
申请号：US12487492
申请日：2009-06-18
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Motoyasu Terao , Kenzo Kurotsuchi , Tsuyoshi Yamauchi
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Motoyasu Terao , Kenzo Kurotsuchi , Tsuyoshi Yamauchi
IPC分类号： H01L47/00
CPC分类号： H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.
摘要翻译：通过高速非易失性相变存储器，提高了刷新次数的可靠性。在使用MISFET作为选择存储单元的晶体管的相变存储器的存储单元形成区域中，形成了使用相变材料的包括电阻元件的存储单元的相变材料层，用于常用。结果，减少了通过蚀刻对存储单元元件的隔离而导致的相变材料的形状变化和组成变化，从而提高了存储单元的刷新次数的可靠性。

3. 发明授权

US07996735B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07996735B2
公开(公告)日：2011-08-09
申请号：US12469778
申请日：2009-05-21
申请人： Motoyasu Terao , Satoru Hanzawa , Hitoshi Kume , Minoru Ogushi , Yoshitaka Sasago , Masaharu Kinoshita , Norikatsu Takaura
发明人： Motoyasu Terao , Satoru Hanzawa , Hitoshi Kume , Minoru Ogushi , Yoshitaka Sasago , Masaharu Kinoshita , Norikatsu Takaura
IPC分类号： G11C29/00
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C29/028 , G11C29/50 , G11C29/50008 , G11C2013/0054 , G11C2213/72
摘要： To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.
摘要翻译：为了实现低功耗的快速且高度可靠的相变存储器系统，半导体器件包括：存储器件，其包括具有包括多个第一存储器单元的第一区域的第一存储器阵列和包括多个第一存储器单元的第二区域第二存储单元; 控制器，其耦合到所述存储器设备以向所述存储器设备发出命令; 以及用于存储多个试写条件的条件表。控制器基于存储在条件表中的多个试写条件，在多个第二存储单元中执行多次尝试写入，并且基于试写的结果来确定多个第一存储单元中的写入条件。存储器件基于从控制器指示的写入条件在多个第一存储器单元中执行写入。

4. 发明授权

US07834337B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US07834337B2
公开(公告)日：2010-11-16
申请号：US10587079
申请日：2004-12-20
申请人： Norikatsu Takaura , Motoyasu Terao , Hideyuki Matsuoka , Kenzo Kurotsuchi
发明人： Norikatsu Takaura , Motoyasu Terao , Hideyuki Matsuoka , Kenzo Kurotsuchi
IPC分类号： H01L29/02
CPC分类号： G11C13/0004 , G11C13/04 , G11C13/047 , G11C2213/56 , G11C2213/71 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1625
摘要： A phase-change memory device including a memory cell having a memory element and a select transistor is improved in heat resistance so that it may be operable at 145° C. or higher.The memory layer is used which has a content of Zn or Cd of 20 at % or more and 50 at % or less, a content of Ge or Sb of 5 at % or more and 25 at % or less, and a content of Te of 40 at % or more and 65 at % or less in Zn-Ge-Te.
摘要翻译：包括具有存储元件和选择晶体管的存储单元的相变存储器件的耐热性得到改善，使得其在145℃以上可操作。使用具有20原子％以上且50原子％以下的Zn或Cd含量的记忆层，Ge或Sb的含量为5原子％以上且25原子％以下，Te含量在Zn-Ge-Te中为40at％以上且65at％以下。

5. 发明申请

US20100061132A1 SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：半导体存储设备
公开(公告)号：US20100061132A1
公开(公告)日：2010-03-11
申请号：US12516690
申请日：2006-12-07
申请人： Yoshihisa Fujisaki , Satoru Hanzawa , Kenzo Kurotsuchi , Nozomu Matsuzaki , Norikatsu Takaura
发明人： Yoshihisa Fujisaki , Satoru Hanzawa , Kenzo Kurotsuchi , Nozomu Matsuzaki , Norikatsu Takaura
IPC分类号： G11C11/00 , H01L45/00 , G11C5/02 , G11C7/00
CPC分类号： H01L45/144 , G11C13/0004 , G11C13/0069 , G11C2213/75 , H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233
摘要： In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided. The semiconductor storage device includes a phase change thin film 101 having two stable phases of a crystal state with low electric resistance and an amorphous state with high electric resistance, upper plug electrodes 102 and 103 provided on one side of the phase change thin film 101, a lower electrode 104 provided on the other side of the phase change thin film 101, a selecting transistor 114 whose drain/source terminals are connected to the upper plug electrode 102 and the lower electrode 104, and a selecting transistor 115 whose drain/source terminals are connected to the upper plug electrode 103 and the lower electrode 104, and a first memory cell is configured with the selecting transistor 114 and a phase change region 111 in the phase change thin film 101 sandwiched between the upper plug electrode 102 and the lower electrode 104, and a second memory cell is configured with the selecting transistor 115 and a phase change region 112 in the phase change thin film 101 sandwiched between the upper plug electrode 103 and the lower electrode 104.
摘要翻译：在诸如相变存储器的半导体存储装置中，提供了可以实现高集成度的技术。半导体存储装置包括：具有低电阻的晶体状态的两个稳定相和具有高电阻的非晶态的相变薄膜101，设置在相变薄膜101一侧的上部插塞电极102和103，设置在相变薄膜101的另一侧的下部电极104，漏极/源极端子连接到上部插塞电极102和下部电极104的选择晶体管114，以及选择晶体管115，其漏极/源极端子连接到上插头电极103和下电极104，并且第一存储单元配置有夹在上插头电极102和下电极之间的相变薄膜101中的选择晶体管114和相变区域111 104，并且第二存储单元配置有夹在b中的相变薄膜101中的选择晶体管115和相变区域112 在上塞电极103和下电极104之间。

6. 发明申请

US20090052231A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20090052231A1
公开(公告)日：2009-02-26
申请号：US12162702
申请日：2006-02-02
申请人： Kenzo Kurotsuchi , Norikatsu Takaura , Yoshihisa Fujisaki
发明人： Kenzo Kurotsuchi , Norikatsu Takaura , Yoshihisa Fujisaki
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0073 , G11C2013/0078 , G11C2213/79 , H01L27/24
摘要： A semiconductor device capable of high-speed read and has a high data-retention characteristic is provided. In a semiconductor device including a memory array having a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, where each memory cell includes an information memory section and a select element, when information is programmed by a first pulse (reset operation) for programming information flowing in the bit line and a second pulse (set operation) different from the first pulse and information is read by a third pulse (read operation), current directions of the second pulse and the third pulse are opposite to each other.
摘要翻译：提供了一种能够高速读取并具有高数据保持特性的半导体器件。在包括具有设置在多个字线和多个位线的交叉点处的多个存储单元的存储器阵列的半导体器件中，其中每个存储单元包括信息存储器部分和选择元件，当信息由用于编程在位线中流动的信息的第一脉冲（复位操作）和与第一脉冲和信息不同的第二脉冲（置位操作）被第三脉冲（读操作）读取，第二脉冲和第三脉冲脉冲彼此相反。

7. 发明授权

US07470923B2 Semiconductor integrated circuit device 有权
公开(公告)号：US07470923B2
公开(公告)日：2008-12-30
申请号：US11370945
申请日：2006-03-09
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Motoyasu Terao , Kenzo Kurotsuchi , Tsuyoshi Yamauchi
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Motoyasu Terao , Kenzo Kurotsuchi , Tsuyoshi Yamauchi
IPC分类号： H01L47/00
CPC分类号： H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.

8. 发明授权

US07385838B2 Semiconductor device with a non-erasable memory and/or a nonvolatile memory 失效
标题翻译：具有不可擦除存储器和/或非易失性存储器的半导体器件
公开(公告)号：US07385838B2
公开(公告)日：2008-06-10
申请号：US11715918
申请日：2007-03-09
申请人： Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
发明人： Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
摘要翻译：一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。

9. 发明申请

US20080089154A1 Memory device 审中-公开
标题翻译：内存设备
公开(公告)号：US20080089154A1
公开(公告)日：2008-04-17
申请号：US11952540
申请日：2007-12-07
申请人： Motoyasu Terao , Norikatsu Takaura , Kenzp Kurotsuchi , Hideyuki Matsuoka , Tsuyoshi Yamauchi
发明人： Motoyasu Terao , Norikatsu Takaura , Kenzp Kurotsuchi , Hideyuki Matsuoka , Tsuyoshi Yamauchi
IPC分类号： G11C7/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1213 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/144 , H01L45/1625
摘要： A memory device is provided which includes a substrate, lower electrodes, selecting elements, memory elements formed of chalcogenide material and upper electrodes. The selecting elements and the memory elements are arranged to be disposed between the upper electrodes and the lower electrodes. In addition, the lower electrodes, the memory elements and the upper electrodes are disposed along lines perpendicular to the substrate surface when the memory device is viewed in a first direction.
摘要翻译：提供了一种存储器件，其包括衬底，下电极，选择元件，由硫族化物材料形成的存储元件和上电极。选择元件和存储元件布置成设置在上电极和下电极之间。此外，当沿第一方向观察存储器件时，下电极，存储元件和上电极沿垂直于衬底表面的线设置。

10. 发明申请

US20060274593A1 Semiconductor integrated circuit device 失效
公开(公告)号：US20060274593A1
公开(公告)日：2006-12-07
申请号：US11501118
申请日：2006-08-09
申请人： Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
发明人： Kenzo Kurotsuchi , Norikatsu Takaura , Osamu Tonomura , Motoyasu Terao , Hideyuki Matsuoka , Riichiro Takemura
IPC分类号： G11C17/18
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0071 , G11C2013/0078 , G11C2013/009 , G11C2213/76 , G11C2213/79
摘要： In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式