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1. 发明申请

US20140013070A1 DYNAMIC MEMORY PERFORMANCE THROTTLING 有权
标题翻译：动态记忆性能曲线
公开(公告)号：US20140013070A1
公开(公告)日：2014-01-09
申请号：US13997977
申请日：2011-12-23
申请人： Brian Toronyi , Kenneth Shoemaker
发明人： Brian Toronyi , Kenneth Shoemaker
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F13/1668 , G11C5/025 , G11C7/04 , G11C7/10 , G11C11/402 , G11C11/406 , G11C11/4063 , G11C11/4076 , G11C11/4096 , G11C2207/2254
摘要： Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements; the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank, and, upon determining that misaligment between the first rank and the second rank is greater than a threshold, the memory controller is to insert a time shift between a data signal for the first rank and a data signal for the second rank.
摘要翻译：动态内存性能调节。存储器件的实施例包括包括耦合的存储器元件的存储器堆栈; 所述存储器元件包括多个等级，所述多个等级包括第一等级和第二等级，以及包括存储器控制器的逻辑器件。存储器控制器用于确定与第一等级的读取请求相关的数据信号与第二等级的读取请求之间的未对准的量，并且在确定第一等级和第二等级之间的错位大于阈值时存储器控制器将在第一等级的数据信号和第二等级的数据信号之间插入时移。

2. 发明授权

US08971087B2 Stacked memory with interface providing offset interconnects 有权
标题翻译：具有提供偏移互连的接口的堆叠存储器
公开(公告)号：US08971087B2
公开(公告)日：2015-03-03
申请号：US13997148
申请日：2011-12-02
申请人： Pete Vogt , Andre Schaefer , Warren Morrow , John Halbert , Jin Kim , Kenneth Shoemaker
发明人： Pete Vogt , Andre Schaefer , Warren Morrow , John Halbert , Jin Kim , Kenneth Shoemaker
IPC分类号： G11C5/06 , H01L27/108 , H01L25/065 , H01L23/48 , H01L23/00
CPC分类号： H01L25/0657 , G11C5/06 , H01L23/481 , H01L24/16 , H01L27/108 , H01L27/10882 , H01L27/10897 , H01L2224/16146 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541
摘要： Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.
摘要翻译：用于具有提供偏移互连的接口的堆叠存储器的操作的动态操作。存储器件的实施例包括与系统元件耦合的系统元件和存储器堆栈，存储器堆栈包括一个或多个存储器管芯层。每个存储器管芯层包括第一面和第二面，每个存储管芯层的第二面包括用于将存储管芯层的数据接口引脚与耦合元件的第一面的数据接口引脚耦合的接口。每个存储器管芯层的接口包括在存储管芯层的每个数据接口引脚和耦合元件的数据接口引脚的相应数据接口引脚之间提供偏移的连接。

3. 发明申请

US20140140156A1 MEMORY OPERATIONS USING SYSTEM THERMAL SENSOR DATA 有权
标题翻译：使用系统热传感器数据的存储器操作
公开(公告)号：US20140140156A1
公开(公告)日：2014-05-22
申请号：US13997975
申请日：2011-12-23
申请人： Kenneth Shoemaker , Paul Fahey
发明人： Kenneth Shoemaker , Paul Fahey
IPC分类号： G11C11/406
CPC分类号： G11C11/40626 , G06F1/206 , G11C5/025 , G11C7/04 , G11C11/406 , G11C11/40615 , G11C2211/4067 , H01L2224/16145 , H01L2224/16225 , H01L2924/15311 , H01L2924/181 , H01L2924/00012
摘要： Memory operations using system thermal sensor data. An embodiment of a memory device includes a memory stack including one or more coupled memory elements, and a logic chip coupled with the memory stack, the logic chip including a memory controller and one or more thermal sensors, where the one or more thermal sensors include a first thermal sensor located in a first area of the logic chip. The memory controller obtains thermal values of the one or more thermal sensors, where the logic element is to estimate thermal conditions for the memory stack using the thermal values, the determination of the estimated thermal conditions for the memory stack being based at least in part on a location of the first thermal sensor in the first area of the logic element. A refresh rate for one or more portions of the memory stack is modified based at least in part on the estimated thermal conditions for the memory stack.
摘要翻译：使用系统热传感器数据进行存储操作。存储器件的一个实施例包括存储器堆叠，其包括一个或多个耦合的存储器元件，以及与存储器堆叠耦合的逻辑芯片，逻辑芯片包括存储器控制器和一个或多个热传感器，其中一个或多个热传感器包括位于逻辑芯片的第一区域中的第一热传感器。存储器控制器获得一个或多个热传感器的热值，其中逻辑元件将使用热值来估计存储器堆的热条件，至少部分地基于对存储器堆的估计热条件的确定第一热传感器位于逻辑元件的第一区域中。至少部分地基于用于存储器堆栈的估计的热条件来修改存储器堆栈的一个或多个部分的刷新率。

4. 发明申请

US20130292840A1 STACKED MEMORY ALLOWING VARIANCE IN DEVICE INTERCONNECTS 有权
标题翻译：在设备互连中容纳变化的堆叠存储器
公开(公告)号：US20130292840A1
公开(公告)日：2013-11-07
申请号：US13997152
申请日：2011-12-02
申请人： Kenneth Shoemaker , Pete Vogt
发明人： Kenneth Shoemaker , Pete Vogt
IPC分类号： H01L25/065
CPC分类号： H01L25/0657 , H01L23/147 , H01L23/481 , H01L25/0652 , H01L25/18 , H01L27/108 , H01L27/10882 , H01L27/10897 , H01L2225/06527 , H01L2225/06541 , H01L2225/06565 , H01L2924/0002 , H01L2924/00
摘要： A stacked memory allowing variance in device interconnects. An embodiment of a memory device includes a system element for the memory device, the system element including multiple pads, and a memory stack connected with the system element, the memory stack having one or more memory die layers, a connection of the system element and the memory stack including interconnects for connecting a first memory die layer and the plurality of pads of the system element. For a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack, and for two or more memory die layers, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack.
摘要翻译：堆叠的存储器允许器件互连方面的差异。存储器件的实施例包括用于存储器件的系统元件，所述系统元件包括多个焊盘，以及与所述系统元件连接的存储器堆栈，所述存储器堆栈具有一个或多个存储器管芯层，所述系统元件和存储器堆叠包括用于连接第一存储器管芯层和系统元件的多个焊盘的互连。对于存储器堆栈中的单个存储器管芯层，多个衬垫的第一子集用于用于系统元件和存储器堆叠的连接的第一组互连，并且对于两个或更多个存储器管芯层，第一组子集和多个焊盘的另外的第二子集被用于第一组互连和用于系统元件和存储器堆的连接的第二组互连。

5. 发明授权

US6088793A Method and apparatus for branch execution on a multiple-instruction-set-architecture microprocessor 失效
标题翻译：在多指令集架构微处理器上执行分支的方法和装置
公开(公告)号：US6088793A
公开(公告)日：2000-07-11
申请号：US777237
申请日：1996-12-30
申请人： Kin-Yip Liu , Millind Mital , Kenneth Shoemaker
发明人： Kin-Yip Liu , Millind Mital , Kenneth Shoemaker
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3844
摘要： A microprocessor capable of predicting program branches includes a fetching unit, a branch prediction unit, and a decode unit. The fetching unit is configured to retrieve program instructions, including macro branch instructions. The branch prediction unit is configured to receive the program instructions from the fetching unit, analyze the program instructions to identify the macro branch instructions, determine a first branch prediction for each of the macro branch instructions, and direct the fetching unit to retrieve the program instructions in an order corresponding to the first branch predictions. The decode unit is configured to receive the program instructions in the order determined by the branch prediction unit, break down the program instructions into micro-operations, and determine a decoded branch micro-operation corresponding to each of the macro branch instructions requiring verification, such that each of the decoded branch micro-operations has a decoded branch outcome of taken, if the first branch prediction is incorrect, and not taken if the first branch prediction is correct. The microprocessor may also include an execution engine configured to execute the micro-operations and determine the decoded branch outcome for each of the decoded branch micro-operations and communicate each decoded branch outcome of taken to the fetching unit such that the fetching unit can re-retrieve the program instructions in a corrected order corresponding to each incorrect first branch prediction.
摘要翻译：能够预测程序分支的微处理器包括取出单元，分支预测单元和解码单元。提取单元被配置为检索程序指令，包括宏分支指令。分支预测单元被配置为从提取单元接收程序指令，分析程序指令以识别宏分支指令，确定每个宏分支指令的第一分支预测，并且指示提取单元检索程序指令以与第一分支预测相对应的顺序。解码单元被配置为以由分支预测单元确定的顺序接收程序指令，将程序指令分解为微操作，并且确定与需要验证的每个宏分支指令相对应的解码分支微操作，如果第一分支预测不正确，则每个解码分支微操作具有解码的分支结果，如果第一分支预测是正确的，则不采用。微处理器还可以包括执行引擎，其被配置为执行微操作并且为每个解码的分支微操作确定解码的分支结果，并将采集的每个解码的分支结果传送到取出单元，以对应于每个不正确的第一分支预测的校正顺序检索程序指令。

6. 发明授权

US5586276A End bit markers for indicating the end of a variable length instruction to facilitate parallel processing of sequential instructions 失效
标题翻译：用于指示可变长度指令的结束以便于顺序指令的并行处理的结束位标记
公开(公告)号：US5586276A
公开(公告)日：1996-12-17
申请号：US301313
申请日：1994-09-06
申请人： Edward Grochowski , Kenneth Shoemaker
发明人： Edward Grochowski , Kenneth Shoemaker
IPC分类号： G06F9/32 , G06F9/30 , G06F9/38 , G06F9/00
CPC分类号： G06F9/30152 , G06F9/3816 , G06F9/3885
摘要： Apparatus for determining the length of an instruction being processed by a computer system when instructions vary in length and appear sequentially in an instruction stream without differentiation between instructions including apparatus for providing an end bit for each predesignated length of an instruction to indicate that the instruction ends at that point in its length, apparatus for setting the end bit at the particular predesignated length of the instruction which is the actual end of the instruction, a first channel for processing a first instruction in sequence, a second channel for processing an instruction next following the first instruction, and apparatus for looking at the end bits of an instruction being processed by the first channel to determine the end point of that instruction and the beginning of the next instruction from the stream of instructions.
摘要翻译：用于当指令长度变化并且顺序地出现在指令流中时确定由计算机系统处理的指令的长度的装置，而不区分指令，包括用于为指令的每个预定指定长度提供结束位的装置，以指示指令结束在其长度的那一点上，用于将作为指令的实际结束的指令的特定预定长度的结束位设置用于依次处理第一指令的第一通道，用于处理下一个指令的第二通道第一指令和用于查看由第一通道正在处理的指令的结束位的装置，以从指令流确定该指令的终点和下一个指令的开始。

7. 发明授权

US09627357B2 Stacked memory allowing variance in device interconnects 有权
公开(公告)号：US09627357B2
公开(公告)日：2017-04-18
申请号：US13997152
申请日：2011-12-02
申请人： Kenneth Shoemaker , Pete Vogt
发明人： Kenneth Shoemaker , Pete Vogt
IPC分类号： H01L25/00 , H01L25/065 , H01L27/108 , H01L25/18 , H01L23/48 , H01L23/14
CPC分类号： H01L25/0657 , H01L23/147 , H01L23/481 , H01L25/0652 , H01L25/18 , H01L27/108 , H01L27/10882 , H01L27/10897 , H01L2225/06527 , H01L2225/06541 , H01L2225/06565 , H01L2924/0002 , H01L2924/00
摘要： A stacked memory allowing variance in device interconnects. An embodiment of a memory device includes a system element for the memory device, the system element including multiple pads, and a memory stack connected with the system element, the memory stack having one or more memory die layers, a connection of the system element and the memory stack including interconnects for connecting a first memory die layer and the plurality of pads of the system element. For a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack, and for two or more memory die layers, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack.

8. 发明授权

US09396787B2 Memory operations using system thermal sensor data 有权
标题翻译：使用系统热传感器数据进行存储操作
公开(公告)号：US09396787B2
公开(公告)日：2016-07-19
申请号：US13997975
申请日：2011-12-23
申请人： Kenneth Shoemaker , Paul Fahey
发明人： Kenneth Shoemaker , Paul Fahey
IPC分类号： G11C7/04 , G11C11/406 , G06F1/20 , G11C5/02
CPC分类号： G11C11/40626 , G06F1/206 , G11C5/025 , G11C7/04 , G11C11/406 , G11C11/40615 , G11C2211/4067 , H01L2224/16145 , H01L2224/16225 , H01L2924/15311 , H01L2924/181 , H01L2924/00012
摘要： Memory operations using system thermal sensor data. An embodiment of a memory device includes a memory stack including one or more coupled memory elements, and a logic chip coupled with the memory stack, the logic chip including a memory controller and one or more thermal sensors, where the one or more thermal sensors include a first thermal sensor located in a first area of the logic chip. The memory controller obtains thermal values of the one or more thermal sensors, where the logic element is to estimate thermal conditions for the memory stack using the thermal values, the determination of the estimated thermal conditions for the memory stack being based at least in part on a location of the first thermal sensor in the first area of the logic element. A refresh rate for one or more portions of the memory stack is modified based at least in part on the estimated thermal conditions for the memory stack.
摘要翻译：使用系统热传感器数据进行存储操作。存储器件的一个实施例包括存储器堆叠，其包括一个或多个耦合的存储器元件，以及与存储器堆叠耦合的逻辑芯片，逻辑芯片包括存储器控制器和一个或多个热传感器，其中一个或多个热传感器包括位于逻辑芯片的第一区域中的第一热传感器。存储器控制器获得一个或多个热传感器的热值，其中逻辑元件将使用热值来估计存储器堆的热条件，至少部分地基于对存储器堆的估计热条件的确定逻辑元件的第一区域中的第一热传感器的位置。至少部分地基于用于存储器堆栈的估计的热条件来修改存储器堆栈的一个或多个部分的刷新率。

9. 发明授权

US5978900A Renaming numeric and segment registers using common general register pool 失效
标题翻译：使用公共通用寄存器池重命名数字和段寄存器
公开(公告)号：US5978900A
公开(公告)日：1999-11-02
申请号：US774744
申请日：1996-12-30
申请人： Kin-Yip Liu , Gary Hammond , Kenneth Shoemaker , Anand Pai
发明人： Kin-Yip Liu , Gary Hammond , Kenneth Shoemaker , Anand Pai
IPC分类号： G06F9/30 , G06F9/38 , G06F9/34
CPC分类号： G06F9/3838 , G06F9/30101 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A microprocessor capable of renaming a numeric register and a segment register includes a plurality of general registers and a data dependency unit. The data dependency unit is configured to receive instructions to be executed, wherein the instructions include accessing the numeric register and accessing the segment register. The data dependency unit renames the numeric register as one of the plurality of general registers for each of the instructions accessing said numeric register, renames the segment register as one of the plurality of general registers for each of the instructions accessing the segment register, and generates a dependency vector for each of the instructions. The microprocessor may include a scheduler configured to receive the instructions and dependency vector and schedule the instructions for execution based on the dependency vector, and an execution engine adapted to receive the instructions from the scheduler and execute the instructions.
摘要翻译：能够重命名数字寄存器和段寄存器的微处理器包括多个通用寄存器和数据依赖单元。数据依赖单元被配置为接收要执行的指令，其中指令包括访问数字寄存器和访问段寄存器。数据依赖单元将数字寄存器重命名为访问所述数字寄存器的每个指令的多个通用寄存器之一，将段寄存器重命名为访问段寄存器的每个指令的多个通用寄存器之一，并且生成每个指令的依赖向量。微处理器可以包括被配置为接收指令和依赖性向量的调度器，并且基于依赖性向量调度用于执行的指令，以及适于从调度器接收指令并执行指令的执行引擎。

10. 发明授权

US09104540B2 Dynamic memory performance throttling 有权
标题翻译：动态内存性能调节
公开(公告)号：US09104540B2
公开(公告)日：2015-08-11
申请号：US13997977
申请日：2011-12-23
申请人： Brian Toronyi , Kenneth Shoemaker
发明人： Brian Toronyi , Kenneth Shoemaker
IPC分类号： G06F12/00 , G11C11/402 , G11C11/406 , G11C11/4063 , G11C7/04 , G11C7/10 , G11C11/4076 , G11C11/4096 , G11C5/02
CPC分类号： G06F12/00 , G06F13/1668 , G11C5/025 , G11C7/04 , G11C7/10 , G11C11/402 , G11C11/406 , G11C11/4063 , G11C11/4076 , G11C11/4096 , G11C2207/2254
摘要： Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements; the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank, and, upon determining that misalignment between the first rank and the second rank is greater than a threshold, the memory controller is to insert a time shift between a data signal for the first rank and a data signal for the second rank.
摘要翻译：动态内存性能调节。存储器件的实施例包括包括耦合的存储器元件的存储器堆栈; 所述存储器元件包括多个等级，所述多个等级包括第一等级和第二等级，以及包括存储器控制器的逻辑器件。存储器控制器用于确定与第一等级的读请求相关的数据信号与第二等级的读请求之间的未对准量，并且在确定第一等级和第二等级之间的未对准大于阈值时存储器控制器将在第一等级的数据信号和第二等级的数据信号之间插入时移。

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