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1. 发明授权

US08417943B2 Method and apparatus for performing an authentication after cipher operation in a network processor 失效
公开(公告)号：US08417943B2
公开(公告)日：2013-04-09
申请号：US13270532
申请日：2011-10-11
申请人： Jaroslaw J. Sydir , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Woolrich
发明人： Jaroslaw J. Sydir , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Woolrich
IPC分类号： H04L29/06
CPC分类号： H04L63/0485 , H04L9/0643 , H04L63/12 , H04L2209/125
摘要： A method and apparatus is described for processing of network data packets by a network processor having cipher processing cores and authentication processing cores which operate on data within the network data packets, in order to provide a one-pass ciphering and authentication processing of the network data packets.

2. 发明授权

US08068566B2 Unified multi-mode receiver detector 有权
标题翻译：统一多模接收机检测器
公开(公告)号：US08068566B2
公开(公告)日：2011-11-29
申请号：US11888228
申请日：2007-07-31
申请人： Raghavan Sudhakar , Veerendra Bhora , Kamal J. Koshy
发明人： Raghavan Sudhakar , Veerendra Bhora , Kamal J. Koshy
IPC分类号： H03D1/00
CPC分类号： H04L5/0023 , H04L1/0054 , H04L1/0631 , H04L1/0643
摘要： In general, in one aspect, the disclosure describes a unified simplified maximum likelihood detector to be utilized with multiple input multiple output (MIMO) receivers to estimate transmitted signals. The unified detector includes a common framework capable of being utilized for multiple detection modes and multiple MIMO configurations.
摘要翻译：通常，在一个方面，本公开描述了将与多输入多输出（MIMO）接收机一起使用的统一简化最大似然检测器来估计发射信号。统一检测器包括能够被用于多个检测模式和多个MIMO配置的公共框架。

3. 发明授权

US08065678B2 Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor 有权
标题翻译：用于在可编程网络处理器中调度由密码算法核心执行的命令的处理的方法和装置
公开(公告)号：US08065678B2
公开(公告)日：2011-11-22
申请号：US12380575
申请日：2009-02-27
申请人： Jaroslaw J. Sydir , Chen-Chi Kuo , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
发明人： Jaroslaw J. Sydir , Chen-Chi Kuo , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
IPC分类号： G06F9/46
CPC分类号： G06F9/505 , G06F9/5033
摘要： A method and apparatus for scheduling the processing of commands by a plurality of cryptographic algorithm cores in a network processor.
摘要翻译：一种用于通过网络处理器中的多个加密算法核心调度命令处理的方法和装置。

4. 发明申请

US20090034662A1 Unified multi-mode receiver detector 有权
标题翻译：统一多模接收机检测器
公开(公告)号：US20090034662A1
公开(公告)日：2009-02-05
申请号：US11888228
申请日：2007-07-31
申请人： Raghavan Sudhakar , Veerendra Bhora , Kamal J. Koshy
发明人： Raghavan Sudhakar , Veerendra Bhora , Kamal J. Koshy
IPC分类号： H03D1/02
CPC分类号： H04L5/0023 , H04L1/0054 , H04L1/0631 , H04L1/0643
摘要： In general, in one aspect, the disclosure describes a unified simplified maximum likelihood detector to be utilized with multiple input multiple output (MIMO) receivers to estimate transmitted signals. The unified detector includes a common framework capable of being utilized for multiple spatial operational modes and multiple MIMO configurations.
摘要翻译：通常，在一个方面，本公开描述了将与多输入多输出（MIMO）接收机一起使用的统一简化最大似然检测器来估计发射信号。统一检测器包括能够用于多个空间操作模式和多个MIMO配置的公共框架。

5. 发明授权

US06782406B2 Fast CMOS adder with null-carry look-ahead 有权
标题翻译：快速CMOS加法器，带空载预读
公开(公告)号：US06782406B2
公开(公告)日：2004-08-24
申请号：US09877805
申请日：2001-06-07
申请人： Kamal J. Koshy
发明人： Kamal J. Koshy
IPC分类号： G06F750
CPC分类号： G06F7/508
摘要： A null-carry-lookahead adder is configured to generate and propagate a null-carry signal within and through blocks and groups of blocks within the adder. The null-carry signal terminates the effects of a carry input signal beyond the point at which the null-carry signal is generated. By forming rules for generating and propagating null-carry signals through blocks and groups of blocks within the adder, a maximum P-channel stack depth of two can be achieved for a four-bit adder block, thereby substantially improving the speed of the null-carry-lookahead adder, compared to a convention carry-lookahead adder that is based on generating and propagating carry signals within the adder.
摘要翻译：空进位前瞻加法器被配置为在加法器内部和通过块和块组内生成和传播空进位信号。空载入信号终止进位输入信号超过产生空进位信号的点的影响。通过形成用于通过加法器内的块和块组产生和传播空进位信号的规则，对于四位加法器块，可以实现两个最大P信道堆栈深度为2，从而实质上提高零位进位信号的速度，与前置加法器相比，它是基于在加法器内产生和传播进位信号的惯例进位 - 前瞻加法器。

6. 发明授权

US6130559A QMOS digital logic circuits 失效
标题翻译： QMOS数字逻辑电路
公开(公告)号：US6130559A
公开(公告)日：2000-10-10
申请号：US52768
申请日：1998-03-31
申请人： Poras T. Balsara , Kamal J. Koshy
发明人： Poras T. Balsara , Kamal J. Koshy
IPC分类号： H03K19/0948 , H03K19/10 , H03K19/094 , H03K19/082
CPC分类号： B82Y10/00 , H03K19/0948 , H03K19/10
摘要： Circuit designs of basic digital logic gates are disclosed using Resonant Tunneling Diodes (RTDs) and MOSFETs, which reduces the number of devices used for logic design, while exploiting the high speed negative differential resistance (NDR) characteristics of RTDs. Such logic circuits include NAND, NOR, AND, and OR gates and Minority/Majority circuits, which are used in full adder circuits. By implementing RTDs along with conventional MOSFETs, the use of series connected MOSFETs, which results in low output rise and fall times, especially for a large number of inputs, can be avoided. Furthermore, the RTD logic design styles do not require the use of resistors or any elaborate clocking or resetting scheme.
摘要翻译：使用谐振隧道二极管（RTD）和MOSFET公开了基本数字逻辑门的电路设计，这减少了用于逻辑设计的器件数量，同时利用RTD的高速负差分电阻（NDR）特性。这种逻辑电路包括在全加器电路中使用的NAND，NOR，AND和OR门和少数/多数电路。通过与常规MOSFET一起实施RTD，可以避免使用串联连接的MOSFET，这导致低输出上升和下降时间，特别是对于大量输入。此外，RTD逻辑设计样式不需要使用电阻或任何精心设计的时钟或复位方案。

7. 发明申请

US20090287925A1 Method and apparatus for performing an authentication after cipher operation in a network processor 有权
标题翻译：在网络处理器中进行密码操作之后进行认证的方法和装置
公开(公告)号：US20090287925A1
公开(公告)日：2009-11-19
申请号：US12455038
申请日：2009-05-27
申请人： Jaroslaw J. Sydir , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
发明人： Jaroslaw J. Sydir , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
IPC分类号： H04L9/00
CPC分类号： H04L63/0485 , H04L9/0643 , H04L63/12 , H04L2209/125
摘要： A method and apparatus is described for processing of network data packets by a network processor having cipher processing cores and authentication processing cores which operate on data within the network data packets, in order to provide a one-pass ciphering and authentication processing of the network data packets.
摘要翻译：描述了一种方法和装置，用于通过具有对网络数据分组内的数据进行操作的密码处理核和认证处理核的网络处理器来处理网络数据分组，以便提供网络数据的一次通过加密和认证处理数据包

8. 发明申请

US20090271795A1 Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor 有权
公开(公告)号：US20090271795A1
公开(公告)日：2009-10-29
申请号：US12380575
申请日：2009-02-27
申请人： Jaroslaw J. Sydir , Chen-Chi Kuo , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
发明人： Jaroslaw J. Sydir , Chen-Chi Kuo , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
IPC分类号： G06F9/46
CPC分类号： G06F9/505 , G06F9/5033
摘要： A method and apparatus for scheduling the processing of commands by a plurality of cryptographic algorithm cores in a network processor.

9. 发明授权

US07529924B2 Method and apparatus for aligning ciphered data 有权
标题翻译：用于对齐加密数据的方法和装置
公开(公告)号：US07529924B2
公开(公告)日：2009-05-05
申请号：US10749035
申请日：2003-12-30
申请人： Jaroslaw Sydir , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
发明人： Jaroslaw Sydir , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
IPC分类号： H04L9/00
CPC分类号： H04L63/0485 , H04L63/126
摘要： A data processing device includes a crypto unit having an alignment buffer for providing data to transmit buffer elements of a media switch fabric in multiples of a predetermined number of bytes. Ciphered data for a packet can be split over first and second transmit buffer elements so as to reduce the amount of software intervention.
摘要翻译：数据处理装置包括具有对准缓冲器的加密单元，用于以预定数量的字节的倍数提供数据以传送介质交换结构的缓冲器元件。分组的加密数据可以分割在第一和第二发送缓冲器元件上，以便减少软件干预的量。

10. 发明授权

US6124737A Low power clock buffer having a reduced, clocked, pull-down transistor 有权
标题翻译：低功耗时钟缓冲器具有降低时钟的下拉晶体管
公开(公告)号：US6124737A
公开(公告)日：2000-09-26
申请号：US345972
申请日：1999-06-30
申请人： Jiann-Cherng James Lan , Sudarshan Kumar , Kamal J. Koshy
发明人： Jiann-Cherng James Lan , Sudarshan Kumar , Kamal J. Koshy
IPC分类号： H03K19/00 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/0016 , H03K19/01855
摘要： A clock buffer includes a clocked pull-up transistor and a clocked pull-down transistor. The clocked pull-up transistor has a drain coupled to an output line and a gate coupled to a clock signal line. The clocked pull-down transistor includes a drain coupled to the output line, a gate coupled to the clock signal line, and having a width Y. The buffer further includes a first pull-down transistor having a drain coupled to a source of the clocked pull-down transistor, a gate coupled to a first input signal line, and having a width that is at least 10% greater than Y. This clock buffer provides reduced power consumption in comparison to a more conventional clock buffer.
摘要翻译：时钟缓冲器包括时钟上拉晶体管和时钟控制下拉晶体管。时钟上拉晶体管具有耦合到输出线的漏极和耦合到时钟信号线的栅极。时钟控制的下拉晶体管包括耦合到输出线的漏极，耦合到时钟信号线的栅极并具有宽度Y.该缓冲器还包括第一下拉晶体管，其具有耦合到时钟信号源的漏极下拉晶体管，耦合到第一输入信号线的栅极，并且具有比Y大至少10％的宽度。与较传统的时钟缓冲器相比，该时钟缓冲器提供了降低的功耗。

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