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1. 发明申请

US20060174062A1 Method and system for cache utilization by limiting number of pending cache line requests 有权
标题翻译：通过限制待处理高速缓存行请求的数量来实现缓存利用的方法和系统
公开(公告)号：US20060174062A1
公开(公告)日：2006-08-03
申请号：US11049454
申请日：2005-02-02
申请人： John Bockhaus
发明人： John Bockhaus
IPC分类号： G06F12/00
CPC分类号： G06F12/0855 , G06F12/0835 , G06F12/0862
摘要： System and method for memory utilization in a computer system are described. In one embodiment, the method comprises, responsive to receipt of a new cache line-sized memory request, determining whether a number of pending requests is less than a fetch limit that is equal to or less than a number of cache lines of a cache memory; and responsive to a determination that the number of pending requests is less than the fetch limit, performing an arbitration among all of the pending requests, including the new cache line-sized memory request.
摘要翻译：描述了计算机系统中的存储器利用的系统和方法。在一个实施例中，该方法包括：响应于接收到新的高速缓存行大小的存储器请求，确定多个未决请求是否小于等于或小于高速缓存存储器的高速缓存行数量的提取限制 ; 并且响应于所述未决请求的数量小于所述提取限制的确定，在包括所述新的高速缓存行大小的存储器请求的所有未决请求之间执行仲裁。

2. 发明申请

US20060153226A1 Systems and methods for a unified computer system fabric 有权
标题翻译：统一计算机系统架构的系统和方法
公开(公告)号：US20060153226A1
公开(公告)日：2006-07-13
申请号：US10998239
申请日：2004-11-23
申请人： Gary Gostin , Craig Warner , John Bockhaus
发明人： Gary Gostin , Craig Warner , John Bockhaus
IPC分类号： H04L12/66 , H04J3/22
CPC分类号： G06F13/4022
摘要： Disclosed are systems and methods providing a unified system fabric in a computer. The systems and methods of embodiments including first interface disposed between a first component of the computer system and a second component of the computer system, the first interface implementing an interface protocol, and a second interface disposed between the first component of the computer system and a third component of the computer system, the second interface implementing the interface protocol, wherein the first interface and the second interface comprise separate signal paths at the first component.
摘要翻译：公开了在计算机中提供统一的系统结构的系统和方法。实施例的系统和方法包括设置在计算机系统的第一部件和计算机系统的第二部件之间的第一接口，实现接口协议的第一接口和设置在计算机系统的第一部件之间的第二接口和计算机系统的第三组件，实现接口协议的第二接口，其中第一接口和第二接口在第一组件处包括单独的信号路径。

3. 发明申请

US20060184831A1 Passing debug information 有权
标题翻译：传递调试信息
公开(公告)号：US20060184831A1
公开(公告)日：2006-08-17
申请号：US11056505
申请日：2005-02-11
申请人： Gregg Lesartre , John Bockhaus
发明人： Gregg Lesartre , John Bockhaus
IPC分类号： G06F11/00
CPC分类号： G06F11/3632 , G06F11/3648
摘要： A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to generating processing debug information, processing link identification information, injecting errors across communications links and performing error detection.
摘要翻译：采用串行化器和解串器的数据通信架构可以减少数据通信延迟。在说明性实现中，数据通信架构通过通信链路传送数据。该架构维护各种机制，以提升数据通信速度，避免通信链路停机。这些机制执行包括但不限于生成处理调试信息，处理链路识别信息，跨通信链路注入错误并执行错误检测的功能。

4. 发明申请

US20060179175A1 Method and system for cache utilization by limiting prefetch requests 有权
标题翻译：通过限制预取请求来缓存利用的方法和系统
公开(公告)号：US20060179175A1
公开(公告)日：2006-08-10
申请号：US11049024
申请日：2005-02-02
申请人： John Bockhaus , David Binford
发明人： John Bockhaus , David Binford
IPC分类号： G06F13/28
CPC分类号： G06F12/0862
摘要： System and method of memory utilization in a computer system are described. In one embodiment, the method comprises, responsive to receipt of a DMA transaction from an entity, determining whether a number of pending memory requests for the entity is less than a prefetch limit therefor; and responsive to a determination that the number of pending memory requests for the entity is less than the prefetch limit therefor, issuing a new memory request comprising a portion of the received DMA transaction.
摘要翻译：描述了计算机系统中的内存利用的系统和方法。在一个实施例中，该方法包括：响应于从实体接收到DMA事务，确定对于该实体的多个未决存储器请求是否小于其预取限制; 并且响应于确定所述实体的未决存储器请求的数量小于其预取限制，发出包括所接收的DMA事务的一部分的新的存储器请求。

5. 发明申请

US20060179174A1 Method and system for preventing cache lines from being flushed until data stored therein is used 审中-公开
标题翻译：使用用于防止高速缓存行被刷新直到其中存储数据的方法和系统
公开(公告)号：US20060179174A1
公开(公告)日：2006-08-10
申请号：US11049011
申请日：2005-02-02
申请人： John Bockhaus , David Binford
发明人： John Bockhaus , David Binford
IPC分类号： G06F13/28
CPC分类号： G06F12/126 , G06F12/0835 , G06F12/0862 , G06F12/0875 , G06F2212/303
摘要： System and method of memory utilization in a computer system are described. In one embodiment, the method comprises, responsive to receipt of a DMA transaction from an entity, determining whether a memory request comprising a cache line-sized portion of the DMA transaction is speculative; and responsive to a determination that the memory request is not speculative, ensuring that a prefetch lock indicator of a cache line of a cache associated with the memory request is in a locked condition, thereby preventing a cache replacement algorithm (“CRA”) from flushing the associated cache line.
摘要翻译：描述了计算机系统中的内存利用的系统和方法。在一个实施例中，该方法包括响应于从实体接收DMA事务，确定包括DMA事务的高速缓存行大小部分的存储器请求是否是推测性的; 并且响应于所述存储器请求不是推测性的确定，确保与所述存储器请求相关联的高速缓存行的预取锁定指示符处于锁定状态，从而防止高速缓存替换算法（“CRA”）冲洗关联的缓存行。

6. 发明申请

US20060179173A1 Method and system for cache utilization by prefetching for multiple DMA reads 审中-公开
标题翻译：通过预取多个DMA读取来缓存利用的方法和系统
公开(公告)号：US20060179173A1
公开(公告)日：2006-08-10
申请号：US11048830
申请日：2005-02-02
申请人： John Bockhaus
发明人： John Bockhaus
IPC分类号： G06F13/28
CPC分类号： G06F12/1054
摘要： System and method of memory utilization in a computer system are described. In one embodiment, the method comprises storing a DMA transaction received from an entity in a request address first-in, first out buffer (“RAF”); determining whether a first DMA transaction stored in the RAF is a read request; and responsive to a determination that the first DMA transaction is a read request, issuing at least one prefetch memory request in connection with the read request; otherwise, forgoing issuance of at least one prefetch memory request in connection with the first DMA transaction and determining whether a next DMA transaction stored in the RAF is a read request.
摘要翻译：描述了计算机系统中的内存利用的系统和方法。在一个实施例中，该方法包括将从实体接收的DMA事务存储在请求地址先进先出缓冲器（“RAF”）中; 确定存储在所述RAF中的第一DMA事务是否是读请求; 并且响应于所述第一DMA事务是读请求的确定，发出与所述读请求相关联的至少一个预取存储器请求; 否则，将发送与第一DMA事务相关联的至少一个预取存储器请求，并确定存储在RAF中的下一个DMA事务是否为读取请求。

7. 发明申请

US20060026468A1 Crossbar switch debugging 有权
标题翻译：交叉开关调试
公开(公告)号：US20060026468A1
公开(公告)日：2006-02-02
申请号：US11079414
申请日：2005-03-14
申请人： James Greener , Christopher Woody , Robert McFarland , Tyler Johnson , Gregg Lesartre , John Bockhaus
发明人： James Greener , Christopher Woody , Robert McFarland , Tyler Johnson , Gregg Lesartre , John Bockhaus
IPC分类号： G06F11/00
CPC分类号： G06F11/221
摘要： A crossbar switch having a plurality of ports that allows a debug process to be performed on the switch using one of the plurality of ports to output chip status information. The switch uses a debug block to store chip status information.
摘要翻译：具有多个端口的交叉开关，其允许使用所述多个端口中的一个来对所述交换机执行调试处理以输出芯片状态信息。交换机使用调试块来存储芯片状态信息。

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