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1. 发明授权

US06701340B1 Double differential comparator and programmable analog block architecture using same 有权
标题翻译：双差分比较器和可编程模拟块结构使用相同
公开(公告)号：US06701340B1
公开(公告)日：2004-03-02
申请号：US09668896
申请日：2000-09-22
申请人： James L. Gorecki , Bill G. Gazeley , Yaohua Yang
发明人： James L. Gorecki , Bill G. Gazeley , Yaohua Yang
IPC分类号： G06G700
CPC分类号： G06J1/00 , H03H11/04 , H03K5/249
摘要： A double differential comparator can be efficiently implemented utilizing a first comparator stage having a folded cascode with floating gate input terminals and clamped single-ended output, and a capacitively coupled input stage for transferring a weighted sum of input signals to the floating gates of the first comparator stage. Additionally, the double differential comparator can be integrated into fully differential programmable analog integrated circuits. Such fully differential programmable analog integrated circuits can also include a differential output digital-to-analog converter to be used with or without the double differential comparator.
摘要翻译：可以利用具有折叠共源共栅的第一比较器级与浮动栅极输入端和被钳位的单端输出来有效地实现双差分比较器，以及电容耦合输入级，用于将输入信号的加权和传递到第一比较器级。此外，双差分比较器可以集成到全差分可编程模拟集成电路中。这种全差分可编程模拟集成电路还可以包括用于或不使用双差分比较器的差分输出数模转换器。

2. 发明授权

US5493205A Low distortion differential transconductor output current mirror 失效
标题翻译：低失真差分跨导体输出电流镜
公开(公告)号：US5493205A
公开(公告)日：1996-02-20
申请号：US403354
申请日：1995-03-14
申请人： James L. Gorecki
发明人： James L. Gorecki
IPC分类号： G06G7/06 , G05F3/26 , H03F1/08 , H03F3/34 , H03F3/45 , H03H11/04 , G05F3/16 , H03F3/04
CPC分类号： H03F3/45197 , G05F3/262 , H03F1/086 , H03F3/45179 , H03F2203/45048 , H03F2203/45202 , H03F2203/45356 , H03F2203/45466 , H03F2203/45471
摘要： A current mirror for use with a transconductor is disclosed. The current mirror includes an input resistor which changes an input current to a voltage, an output resistor having a value which is scaled with respect to the input resistor, an amplifier which senses the input voltage and the voltage across the output resistor and an output transistor having a gate coupled to the output of the amplifier and a source coupled to the output resistor is disclosed. Such a current mirror advantageously provides a transconductor having low distortion.
摘要翻译：公开了一种用于跨导体的电流镜。电流镜包括将输入电流改变为电压的输入电阻器，具有相对于输入电阻器放大的值的输出电阻器，感测输入电压和输出电阻器两端的电压的放大器以及输出晶体管具有耦合到放大器的输出的栅极和耦合到输出电阻器的源极。这种电流镜有利地提供了具有低失真的跨导体。

3. 发明授权

US5159205A Timing generator circuit including adjustable tapped delay line within phase lock loop to control timing of signals in the tapped delay line 失效
标题翻译：定时发生器电路，包括在相位锁定环路中可调节的延迟线，以控制延迟线中的信号时序
公开(公告)号：US5159205A
公开(公告)日：1992-10-27
申请号：US603900
申请日：1990-10-24
申请人： James L. Gorecki , Michael J. McGowan
发明人： James L. Gorecki , Michael J. McGowan
IPC分类号： H03K3/017 , H03K3/64 , H03K5/15 , H03L7/081
CPC分类号： H03L7/0812 , H03K5/15033
摘要： A circuit for generating a plurality of timing signals includes a plurality of cascade-connected delay cells, each having an input coupled to an output of another, and a plurality of latches. Set inputs of various latches are coupled to outputs of various delay cells to determine times of occurrence of leading edges of various timing pulses. Reset inputs of the various latches are coupled to outputs of various delay cells to determine times of occurrence of trailing edges of various timing pulses. The circuit includes a phase detector having a first input coupled to receive a clock signal and a second input coupled to an output of one of the delay cells to receive a signal indicative of propagation of a logic state through a first group of the delay cells, to produce an adjustment signal indicative of whether the phase of the indicator signal is ahead of or behind the phase of the clock signal. Each of the delay cells increases or decreases propagation time through that delay cell in response to the adjustment signal, so as to cause a time required for the logic state to propagate through all of the delay cells to be equal to a period of the clock signal.
摘要翻译：用于产生多个定时信号的电路包括多个级联连接的延迟单元，每个延迟单元具有耦合到另一个的输出的输入和多个锁存器。各种锁存器的设置输入耦合到各种延迟单元的输出，以确定各种定时脉冲的前沿的出现次数。各种锁存器的复位输入耦合到各种延迟单元的输出，以确定各种定时脉冲的后沿的出现次数。该电路包括相位检测器，其具有耦合以接收时钟信号的第一输入和耦合到延迟单元之一的输出的第二输入，以接收指示逻辑状态通过第一组延迟单元传播的信号，以产生指示指示符信号的相位是否在时钟信号的相位之前或之后的调整信号。每个延迟单元响应于调整信号增加或减少通过该延迟单元的传播时间，从而导致逻辑状态通过所有延迟单元传播所需的时间等于时钟信号的周期。

4. 发明授权

US5084634A Dynamic input sampling switch for CDACS 失效
标题翻译：用于CDACS的动态输入采样开关
公开(公告)号：US5084634A
公开(公告)日：1992-01-28
申请号：US602705
申请日：1990-10-24
申请人： James L. Gorecki
发明人： James L. Gorecki
IPC分类号： G11C27/02 , H03K17/16 , H03K17/687
CPC分类号： H03K17/165 , G11C27/02 , H03K17/161 , H03K2217/0018
摘要： A low distortion capacitor sampling circuit includes a sampling MOSFET, the source electrode of which receives a time-varying input voltage to be sampled. A bootstrap capacitor has a first terminal connected to the gate electrode of the sampling MOSFET and to a first MOSFET that charges the first terminal of the bootstrap capacitor to a first voltage in response to a first control signal. A delayed second control signal is applied to the gate of a second MOSFET the drain electrode of which is connected to a second terminal of the bootstrap capacitor to keep the pulldown MOSFET on until the charging of the sampling capacitor is complete. Then a third control signal turns on a third MOSFET, boosting both terminals of the bootstrap capacitor. The second control signal then turns the third MOSFET off, electrically isolating the gate electrode of the sampling MOSFET. Changes in the time-varying input voltage are coupled by the gate-to-source capacitance of the sampling MOSFET to the gate electrode thereof. The input voltage is simultaneously applied to a source follower circuit, the output of which is coupled by a CMOS transmission gate to the body electrode of the sampling MOSFET. The circuit avoids harmonic distortion due to modulation of channel resistance of the sampling MOSFET by keeping the gate-to-source voltage and the source-to-body electrode voltage independent of the input voltage.
摘要翻译：低失真电容器采样电路包括采样MOSFET，其源极接收要采样的时变输入电压。自举电容器具有连接到采样MOSFET的栅电极的第一端子以及响应于第一控制信号而将自举电容器的第一端子充电到第一电压的第一MOSFET。延迟的第二控制信号被施加到第二MOSFET的栅极，第二MOSFET的漏极连接到自举电容器的第二端子，以保持下拉MOSFET导通，直到采样电容器的充电完成。然后第三个控制信号接通第三个MOSFET，从而升压自举电容的两个端子。第二控制信号然后关断第三个MOSFET，使取样MOSFET的栅极电隔离。时变输入电压的变化通过采样MOSFET的栅极 - 源极电容耦合到其栅电极。输入电压同时施加到源极跟随器电路，其源极跟随器电路的输出通过CMOS传输门耦合到采样MOSFET的体电极。该电路通过保持栅极至源极电压和源极至电极电压与输入电压无关，由于调制采样MOSFET的沟道电阻而避免谐波失真。

5. 发明授权

US4543498A Process insensitive CMOS window detector 失效
标题翻译：过程不敏感的CMOS窗口检测器
公开(公告)号：US4543498A
公开(公告)日：1985-09-24
申请号：US418516
申请日：1982-09-16
申请人： James L. Gorecki
发明人： James L. Gorecki
IPC分类号： G01R19/165 , G01R29/027
CPC分类号： G01R19/16519
摘要： A CMOS window detector provides outputs which indicate whether an input voltage is within a voltage "window". The window detector includes a bias circuit and first and second inverter circuits. A bias current is established by the bias circuit as a function of a reference voltage. The first and second inverter circuits each include a current mirror field effect transistor (FET) and a current control FET connected in a series current path. The current mirror FETs are connected to the bias circuit to provide two different mirror currents. The mirror currents are a function of the bias current and the current mirror FET channel shape factors. The input voltage signal is applied to the gates of the current control FETs of the first and second inverters. The window voltage level of each inverter circuit is independent of the other inverter circuit and is determined as a function of the mirror current and channel shape factor of the current control FET. Logic level outputs taken from first and second inverter circuits indicate whether an input signal voltage is within or outside the window created by the window voltage levels of the two inverter circuits.
摘要翻译： CMOS窗口检测器提供指示输入电压是否在电压“窗口”内的输出。窗口检测器包括偏置电路和第一和第二反相器电路。偏置电路建立偏置电流作为参考电压的函数。第一和第二逆变器电路各自包括电流镜效应晶体管（FET）和连接在串联电流路径中的电流控制FET。电流反射镜FET连接到偏置电路以提供两个不同的反射镜电流。反射镜电流是偏置电流和电流反射镜FET通道形状因子的函数。输入电压信号被施加到第一和第二逆变器的电流控制FET的栅极。每个逆变器电路的窗口电压电平独立于其他逆变器电路，并且被确定为电流控制FET的镜电流和通道形状因子的函数。从第一和第二反相器电路获取的逻辑电平输出指示输入信号电压是否在由两个反相器电路的窗口电压电平产生的窗口内或外。

6. 发明授权

US07720160B1 Phase noise shaping using sigma delta modulation in a timing recovery unit 有权
标题翻译：在定时恢复单元中使用Σ-Δ调制的相位噪声整形
公开(公告)号：US07720160B1
公开(公告)日：2010-05-18
申请号：US11639656
申请日：2006-12-14
申请人： James L. Gorecki , Tong Liu
发明人： James L. Gorecki , Tong Liu
IPC分类号： H04B14/06 , H04L7/00 , H03M1/20
CPC分类号： H04B14/062 , H03L7/0812 , H03L7/093 , H03M3/50 , H03M7/3026 , H04L7/0025 , H04L7/033
摘要： A method and apparatus for converting a high precision digital word into a high precision analog signal is disclosed. A sigma delta modulator applies a digital input signal to a dither signal to generate a combined signal for sampling. A digital-to-analog converter quantizes the combined signal. An analog filter provides a cutoff at a bandwidth of interest to remove out of band quantization noise and signals. An I transfer function and a Q transfer function can be coupled between the sigma delta modulator and the digital-to-analog converter for mapping of the combined signal. The apparatus can also include a phase interpolator for receiving the output signal and outputting a clock recovery phase.
摘要翻译：公开了一种用于将高精度数字字转换成高精度模拟信号的方法和装置。 Σ-Δ调制器将数字输入信号施加到抖动信号以产生用于采样的组合信号。数模转换器对组合信号进行量化。模拟滤波器在感兴趣的带宽上提供截止以去除带外量化噪声和信号。可以在Σ-Δ调制器和数 - 模转换器之间耦合I传递函数和Q传递函数，用于映射组合信号。该装置还可以包括用于接收输出信号并输出时钟恢复阶段的相位插值器。

7. 发明授权

US5617064A Active resistor for stability compensation 失效
公开(公告)号：US5617064A
公开(公告)日：1997-04-01
申请号：US403352
申请日：1995-03-14
申请人： James L. Gorecki
发明人： James L. Gorecki
IPC分类号： G06G7/06 , G05F3/26 , H03F1/08 , H03F3/34 , H03F3/45 , H03H11/04 , H03H11/00
CPC分类号： H03F3/45197 , G05F3/262 , H03F1/086 , H03F3/45179 , H03F2203/45048 , H03F2203/45202 , H03F2203/45356 , H03F2203/45466 , H03F2203/45471
摘要： An active termination resistor is provided within a feedback loop circuit thus advantageously increasing the stability of the feedback loop circuit. In particular, the active termination resistor traces the impedance of the feedback loop such that R(f).congruent.1/GM3(f). The active resistor may also be configured to track the value of the resistor to set the feedback transconductance over process and temperature variations to ensure stability of the feedback loop over these variations.

8. 发明授权

US08031783B1 Phase noise shaping using sigma delta modulation in a timing recovery unit 有权
标题翻译：在定时恢复单元中使用Σ-Δ调制的相位噪声整形
公开(公告)号：US08031783B1
公开(公告)日：2011-10-04
申请号：US12754511
申请日：2010-04-05
申请人： James L. Gorecki , Tong Liu
发明人： James L. Gorecki , Tong Liu
IPC分类号： H04B14/06 , H04L7/00 , H03M1/20
CPC分类号： H04B14/062 , H03L7/0812 , H03L7/093 , H03M3/50 , H03M7/3026 , H04L7/0025 , H04L7/033
摘要： A method and apparatus for converting a high precision digital word into a high precision analog value is disclosed. A sigma delta modulator applies a digital input signal to a dither signal to generate a combined signal for sampling. A digital-to-analog converter quantizes the combined signal. An analog filter provides a cutoff at a bandwidth of interest to remove out of band quantization noise and signals. An I transfer function and a Q transfer function can be coupled between the sigma delta modulator and the digital-to-analog converter for mapping of the combined signal. The apparatus can also include a phase interpolator for receiving the output signal and outputting a clock recovery phase.
摘要翻译：公开了一种用于将高精度数字字转换为高精度模拟值的方法和装置。 Σ-Δ调制器将数字输入信号施加到抖动信号以产生用于采样的组合信号。数模转换器对组合信号进行量化。模拟滤波器在感兴趣的带宽上提供截止以去除带外量化噪声和信号。可以在Σ-Δ调制器和数 - 模转换器之间耦合I传递函数和Q传递函数，用于映射组合信号。该装置还可以包括用于接收输出信号并输出时钟恢复阶段的相位插值器。

9. 发明授权

US06714066B2 Integrated programmable continuous time filter with programmable capacitor arrays 有权
标题翻译：具有可编程电容阵列的集成可编程连续时间滤波器
公开(公告)号：US06714066B2
公开(公告)日：2004-03-30
申请号：US10200645
申请日：2002-07-22
申请人： James L. Gorecki , Yaohua Yang
发明人： James L. Gorecki , Yaohua Yang
IPC分类号： H03K500
CPC分类号： H03H11/1291 , H03H11/04
摘要： A programmable capacitor array including a plurality of user-selectable, numerically weighted capacitors, each of which includes at least one fixed capacitor and one manufacturer-controlled trim capacitor, advantageously provides a variety of selectable capacitance values for a programmable analog integrated circuit. When coupled to a memory, for example a static memory, switches can be controlled that determine whether a particular fixed capacitor (user-selectable) or trim capacitor (manufacturer-selectable) is electrically coupled into the circuit. User access to those portions of memory controlling switches associated with the trim capacitors can be restricted via an I/O interface and security command. Such programmable capacitor arrays allow efficient implementation of user-programmable filter circuits where the user can conveniently program or reprogram a variety of filter parameters.
摘要翻译：一种可编程电容器阵列，包括多个用户可选择的数字加权电容器，每个电容器包括至少一个固定电容器和一个制造商控制的修整电容器，有利地为可编程模拟集成电路提供各种可选择的电容值。当耦合到存储器（例如静态存储器）时，可以控制开关以确定特定固定电容器（用户可选择）或修整电容器（制造商可选择）是否电耦合到电路中。可以通过I / O接口和安全命令限制对与修剪电容器相关联的存储器控制开关的这些部分的用户访问。这种可编程电容器阵列允许用户可编程滤波器电路的有效实现，其中用户可以方便地对各种滤波器参数进行编程或重新编程。

10. 发明授权

US06424209B1 Integrated programmable continuous time filter with programmable capacitor arrays 有权
标题翻译：具有可编程电容阵列的集成可编程连续时间滤波器
公开(公告)号：US06424209B1
公开(公告)日：2002-07-23
申请号：US09507580
申请日：2000-02-18
申请人： James L. Gorecki , Yaohua Yang
发明人： James L. Gorecki , Yaohua Yang
IPC分类号： H03K500
CPC分类号： H03H11/1291 , H03H11/04
摘要： A programmable capacitor array including a plurality of user-selectable, numerically weighted capacitors, each of which includes at least one fixed capacitor and one manufacturer-controlled trim capacitor, advantageously provides a variety of selectable capacitance values for a programmable analog integrated circuit. When coupled to a memory, for example a static memory, switches can be controlled that determine whether a particular fixed capacitor (user-selectable) or trim capacitor (manufacturer-selectable) is electrically coupled into the circuit. User access to those portions of memory controlling switches associated with the trim capacitors can be restricted via an I/O interface and security command. Such programmable capacitor arrays allow efficient implementation of user-programmable filter circuits where the user can conveniently program or reprogram a variety of filter parameters.
摘要翻译：一种可编程电容器阵列，包括多个用户可选择的数字加权电容器，每个电容器包括至少一个固定电容器和一个制造商控制的修整电容器，有利地为可编程模拟集成电路提供各种可选择的电容值。当耦合到存储器（例如静态存储器）时，可以控制开关以确定特定固定电容器（用户可选择）或修整电容器（制造商可选择）是否电耦合到电路中。可以通过I / O接口和安全命令限制对与修剪电容器相关联的存储器控制开关的这些部分的用户访问。这种可编程电容器阵列允许用户可编程滤波器电路的有效实现，其中用户可以方便地对各种滤波器参数进行编程或重新编程。

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