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    • 1. 发明授权
    • Systems and methods of providing error tolerant robust simplex wireless data for systems employing time correlated data transfer
    • 为采用时间相关数据传输的系统提供容错鲁棒单工无线数据的系统和方法
    • US08441396B2
    • 2013-05-14
    • US13156967
    • 2011-06-09
    • Darryl I. ParmetJamal HaqueMark D. DuBois
    • Darryl I. ParmetJamal HaqueMark D. DuBois
    • H03M13/00G01S7/40
    • H04L1/08H04L2001/0096
    • Systems and methods of providing error tolerant robust simplex wireless data for systems employing time correlated data transfer are provided. In one embodiment, a system comprises: sensors that produce samples of time correlated data; and a node coupled to the sensors by a wireless link. The link comprises a primary stream for simplex transmission of data packets, and a secondary stream for simplex transmission of delayed data packets, the delayed data packets a delayed retransmission of the time correlated data. When the node receives a first data packet from a first sensor via the primary stream, the data receiving node check validity. When the first data packet is corrupted, the node validity checks a second data packet received via the secondary stream. When both packets contain corrupted data, the node builds a reconstructed plurality of sequential time correlated data samples based on non-corrupted data samples from within the data packets.
    • 提供了对采用时间相关数据传输的系统提供容错鲁棒单工无线数据的系统和方法。 在一个实施例中,系统包括:产生时间相关数据样本的传感器; 以及通过无线链路耦合到传感器的节点。 链路包括用于数据分组的单工传输的主流,以及用于对延迟的数据分组进行单工传输的次流,延迟的数据分组是时间相关数据的延迟重传。 当节点经由主流从第一传感器接收到第一数据分组时,数据接收节点检查有效性。 当第一数据分组被破坏时,节点有效性检查经由次流接收的第二数据分组。 当两个分组都包含损坏的数据时,该节点基于来自数据分组内的未损坏的数据样本建立重建的多个连续的时间相关数据样本。
    • 2. 发明授权
    • Wireless mesh network for inter-component data communications in satellite systems
    • 无线网状网络用于卫星系统中的组件间数据通信
    • US08121036B2
    • 2012-02-21
    • US12342698
    • 2008-12-23
    • Haiyang LiuJamal HaqueAndrzej Peczalski
    • Haiyang LiuJamal HaqueAndrzej Peczalski
    • G08C15/00
    • H04W40/12H04B7/18597H04L45/24
    • A network system for inter-component communications in an electronic device is disclosed. The system comprises a plurality of components for an electronic device, where each of the components communicates with at least one other component over a communications medium for a wireless mesh network. Each of the components comprises a communications transceiver operable to determine network traffic load levels for an exchange of communication data between the components, and allocate the network traffic between at least one pair of the components over a plurality of wireless links within the wireless mesh network based on potential-field based measurements at each of the components. In addition, each of the communications transceivers share the exchange of the communication data between the components based on a prescribed priority level for allocation of the network traffic.
    • 公开了一种用于电子设备中组件间通信的网络系统。 该系统包括用于电子设备的多个组件,其中每个组件通过用于无线网状网络的通信介质与至少一个其他组件通信。 每个组件包括通信收发器,其可操作以确定用于组件之间的通信数据交换的网络业务负载水平,并且通过无线网状网络内的多个无线链路在至少一对组件之间分配网络业务 在每个组件上进行基于电场的测量。 此外,每个通信收发器基于用于分配网络业务的规定的优先级级别共享组件之间的通信数据的交换。
    • 4. 发明申请
    • SYSTEMS AND METHODS FOR TAMPER RESISTANT MEMORY DEVICES
    • 用于防篡改记忆装置的系统和方法
    • US20100132047A1
    • 2010-05-27
    • US12276940
    • 2008-11-24
    • Manuel I. RodriguezJamal HaqueKeith A. Souders
    • Manuel I. RodriguezJamal HaqueKeith A. Souders
    • G06F12/14
    • G06F12/1416G06F21/554G06F2221/2143
    • Systems and methods for tamper resistant memory devices are provided. In one embodiment, a memory device comprises a memory cell for storing digital data, the memory cell having a plurality of memory addresses accessible for read and write operations through a memory interface; and a tamper detection circuit coupled to the memory cell, the tamper detection circuit comprising: a communications decoder coupled to the memory interface, wherein the communications decoder observes sequences of memory access operations to the memory cell; at least one timer for counting a duration of time; a tamper detect state machine responsive to the communications decoder and the at least one timer; and a data destruct engine responsive to the tamper detection state machine, wherein upon receiving an activation signal from the tamper diction state machine, the data destruct engine overwrites digital data stored in the memory cell.
    • 提供了防篡改存储器件的系统和方法。 在一个实施例中,存储器设备包括用于存储数字数据的存储器单元,所述存储器单元具有可通过存储器接口读取和写入操作的多个存储器地址; 篡改检测电路,其连接到所述存储器单元,所述篡改检测电路包括:耦合到所述存储器接口的通信解码器,其中所述通信解码器观察到所述存储器单元的存储器访问操作的序列; 至少一个计时器的计时器; 响应于所述通信解码器和所述至少一个定时器的篡改检测状态机; 以及响应于篡改检测状态机的数据破坏引擎,其中在从所述篡改辞典状态机接收到激活信号时,所述数据破坏引擎将覆盖存储在所述存储单元中的数字数据。
    • 7. 发明申请
    • ROBUST NETWORKS FOR NON-DISRUPTIVELY DISCONNECTING PERIPHERAL DEVICES
    • 用于非破坏性外围设备的稳健网络
    • US20090122725A1
    • 2009-05-14
    • US11937732
    • 2007-11-09
    • Keith A. SoudersJamal Haque
    • Keith A. SoudersJamal Haque
    • H04L12/28
    • H04L12/40078H04L12/44
    • A network and method for non-disruptively disconnecting communication devices are disclosed. The network includes a primary network unit including a first logical layer, and a plurality of secondary network units. Each secondary network unit of the plurality of secondary network units includes the first logical layer, a second logical layer, and a connector arranged at a junction of the first logical layer and the second logical layer. The network also includes a plurality of electrically conductive links, wherein an electrically conductive link of the plurality of electrically conductive links is connected to the first logical layer of a first network unit at a first end, and to the first logical layer of a second network unit at a second end.
    • 公开了一种用于非中断地断开通信设备的网络和方法。 网络包括包括第一逻辑层和多个辅助网络单元的主网络单元。 多个次要网络单元的每个次要网络单元包括布置在第一逻辑层和第二逻辑层的结点处的第一逻辑层,第二逻辑层和连接器。 网络还包括多个导电链路,其中多个导电链路中的导电链路在第一端连接到第一网络单元的第一逻辑层,并连接到第二网络的第一逻辑层 单位在第二端。
    • 8. 发明申请
    • SYSTEM OF INTEGRATED ENVIRONMENATLLY HARDENED ARCHITECTURE FOR SPACE APPLICATION
    • 用于空间应用的集成环境硬化建筑系统
    • US20080256375A1
    • 2008-10-16
    • US11734482
    • 2007-04-12
    • Jamal HaqueAndrew W. GuyetteEdward R. PradoKeith A. Souders
    • Jamal HaqueAndrew W. GuyetteEdward R. PradoKeith A. Souders
    • G06F1/32B64G1/52G06F13/36H05K9/00G11C7/02G06F1/20
    • G06F11/00
    • An environmentally hardened architecture comprises a hybrid processor, a high speed bus having environmentally-sensitive interfaces, an environmentally hardened bus having environmentally-hardened interfaces, and an environmentally-hardened processor communicatively coupled to an environmentally-sensitive interface of the high speed bus and communicatively coupled to an environmentally-hardened interface of the environmentally hardened bus. The hybrid processor includes an environmentally-hardened processing section and an environmentally-sensitive processing section. At least one environmentally-sensitive interface is configured to pass data to and from the environmentally-sensitive processing section and another environmentally-sensitive interface is configured to pass data to and from the environmentally-hardened processing section of the hybrid processor. An environmentally-hardened interface is configured to pass data to and from the environmentally-hardened processing section of the hybrid processor. The environmentally-hardened processor processes critical applications in the environmentally-hardened processing section of the at least one hybrid processor during an environmental event.
    • 环境坚固的架构包括混合处理器,具有环境敏感界面的高速总线,具有环境硬化接口的环境坚固的总线,以及环境硬化处理器,其通信地耦合到高速总线的环境敏感接口并且可通信地 结合环境坚固的总线的环境坚固的界面。 混合处理器包括环境硬化处理部分和环境敏感处理部分。 至少一个对环境敏感的接口被配置为将数据传送到环境敏感处理部分并且从环境敏感处理部分传出数据,另一个环境敏感接口被配置为将数据传送到混合处理器的环境硬化处理部分和/或从环境硬化处理部分传送数据。 环境坚固的接口被配置为将数据传送到混合处理器的环境硬化处理部分和/或从环境硬化的处理部分传送数据。 环境保护的处理器在环境事件期间处理至少一个混合处理器的环境硬化处理部分中的关键应用。