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1. 发明申请

US20080081426A1 SEMICONDUCTOR DEVICE HAVING MOS VARACTOR AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：具有MOS变压器的半导体器件及其制造方法
公开(公告)号：US20080081426A1
公开(公告)日：2008-04-03
申请号：US11941192
申请日：2007-11-16
申请人： Dae-Hyun Kim , Han-Su OH
发明人： Dae-Hyun Kim , Han-Su OH
IPC分类号： H01L21/20
CPC分类号： H01L27/0808 , H01L27/0811 , H01L29/93 , H01L29/94
摘要： A semiconductor device with having a MOS varactor and methods of fabricating the same are disclosed. The MOS varactor includes a metal gate electrode, an active semiconductor plate interposed between the metal gate electrode and the semiconductor substrate, and a capacitor dielectric layer interposed between the metal gate electrode and the active semiconductor plate. Further, a lower insulating layer insulates the MOS varactor from the semiconductor substrate. According to the present invention, a metal gate electrode is used to reduce poly depletion, thereby increasing a tuning range of the varactor, and to manufacture a reliable metal resistor without the need of an additional photomask.
摘要翻译：公开了具有MOS可变电抗器的半导体器件及其制造方法。 MOS变容二极管包括金属栅极电极，介于金属栅电极和半导体衬底之间的有源半导体板以及置于金属栅电极和有源半导体板之间的电容器介电层。此外，下绝缘层使MOS变容二极管与半导体衬底绝缘。根据本发明，使用金属栅电极来减少多余的耗尽，从而增加变容二极管的调谐范围，并且制造可靠的金属电阻器，而不需要额外的光掩模。

2. 发明授权

US07078775B2 MOS transistor having a mesh-type gate electrode 失效
标题翻译： MOS晶体管具有网状栅电极
公开(公告)号：US07078775B2
公开(公告)日：2006-07-18
申请号：US10797604
申请日：2004-03-11
申请人： Duk-min Yi , Han-su Oh , Chul-ho Chung
发明人： Duk-min Yi , Han-su Oh , Chul-ho Chung
IPC分类号： H01L29/94
CPC分类号： H01L29/4238 , H01L23/4824 , H01L29/41758 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A mesh-shaped gate electrode is located over a surface of a substrate. The mesh-shaped gate electrode includes a plurality of first elongate wirings extending parallel to one another, and a plurality of second elongate wirings extending parallel to one another. The first elongate wirings intersect the second elongate wirings to define an array of gate intersection regions over the surface of the substrate and to further define an array of source/drain regions of the substrate. To reduce gate capacitance, at least one oxide region may be located in the substrate below the mesh-shaped gate electrode. For example, an array of oxide regions may be respectively located below the array of gate intersection regions.
摘要翻译：网状栅极位于基板的表面上方。网状栅电极包括彼此平行延伸的多个第一细长布线以及彼此平行延伸的多个第二细长布线。第一细长布线与第二细长布线相交以限定衬底表面上的栅极交叉区域阵列，并进一步限定衬底的源/漏区阵列。为了减小栅极电容，至少一个氧化物区域可以位于网状栅电极下面的衬底中。例如，氧化物区域的阵列可以分别位于栅极交叉区域阵列的下方。

3. 发明授权

US06476457B2 Semiconductor device with drift layer 有权
标题翻译：具有漂移层的半导体器件
公开(公告)号：US06476457B2
公开(公告)日：2002-11-05
申请号：US09729081
申请日：2000-12-05
申请人： Han Su Oh
发明人： Han Su Oh
IPC分类号： H01L2358
CPC分类号： H01L29/0847 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device includes a semiconductor substrate having a first conductive type impurity, a well having a second conductive type impurity formed in a predetermined region of the semiconductor substrate, a plurality of field oxide layer formed on an upper surface of the semiconductor substrate having the first conductive type impurity and the well having the second conductive type impurity, a gate electrode formed on corresponding portions of the field oxide layer and the well, and a lightly doped first impurity region formed in the well between the gate electrode and the first conductive type impurity region and surrounding the first conductive impurity region from sides and lower portions thereof and relatively lightly doped in comparison to the first conductive type impurity region. The device includes a junction of the lightly doped first impurity region surrounding the first conductive type impurity region is relatively deep in comparison to a junction of the lightly doped first impurity region below the field oxide layer, thereby sufficiently relieving electric field and preventing a hot carrier generation and heightening a junction breakdown voltage.
摘要翻译：半导体器件包括具有第一导电类型杂质的半导体衬底，形成在半导体衬底的预定区域中的具有第二导电类型杂质的阱，形成在半导体衬底的上表面上的多个场氧化物层，导电型杂质和具有第二导电类型杂质的阱，形成在场氧化物层和阱的对应部分上的栅电极以及形成在阱电极和第一导电类型杂质之间的阱中的轻掺杂的第一杂质区并且与第一导电类型杂质区相比，从其侧部和下部围绕第一导电杂质区并且相对轻掺杂。该装置包括与第一导电类型杂质区域相邻的轻掺杂的第一杂质区域与场氧化物层下面的轻掺杂的第一杂质区域的结相比较深的结点，由此充分减轻电场并防止热载流子产生并提高结击穿电压。

4. 发明授权

US06448611B1 High power semiconductor device and fabrication method thereof 有权
标题翻译：大功率半导体器件及其制造方法
公开(公告)号：US06448611B1
公开(公告)日：2002-09-10
申请号：US09588546
申请日：2000-06-06
申请人： Han-Su Oh
发明人： Han-Su Oh
IPC分类号： H01L2976
CPC分类号： H01L29/402 , H01L29/0847 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A high power semiconductor device and its fabrication method in which source and the drain regions are spaced apart from and edge of a field oxide layer. This allows the junction profile to become gently-sloped so that the junction breakdown voltage is increased. Also, since the edge of the field oxide layer is covered by the field plate and a ground voltage or below the ground voltage is applied to the field plate, the distribution of the strong electric field formed at the edge of the field oxide layer is dispersed, to further increase the junction breakdown voltage. Moreover, since the field plate covers the field oxide layer at the side of the drain of the high power semiconductor device, when a high voltage is applied to the drain, the electric field distribution is dispersed, so that the junction breakdown voltage at the edge of the gate electrode at the side of the drain can be increased.
摘要翻译：一种高功率半导体器件及其制造方法，其中源极和漏极区域与场氧化物层间隔开和边缘。这允许结型材变得轻轻地倾斜，使得结击穿电压增加。此外，由于场氧化物层的边缘被场板覆盖，并且接地电压或接地电压以下施加到场板，所以形成在场氧化物层的边缘处的强电场的分布被分散，进一步增加结击穿电压。此外，由于场板覆盖大功率半导体器件的漏极侧的场氧化物层，当向漏极施加高电压时，电场分布被分散，使得边缘处的结击穿电压可以增加漏极侧的栅电极。

5. 发明申请

US20170077097A1 SEMICONDUCTOR DEVICE HAVING FIRST AND SECOND GATE ELECTRODES AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有第一和第二栅极电极的半导体器件及其制造方法
公开(公告)号：US20170077097A1
公开(公告)日：2017-03-16
申请号：US15010327
申请日：2016-01-29
申请人： YAOQI DONG , Mun Hyeon Kim , Keun Hwi Cho , Shigenobu Maeda , Han Su Oh
发明人： YAOQI DONG , Mun Hyeon Kim , Keun Hwi Cho , Shigenobu Maeda , Han Su Oh
IPC分类号： H01L27/092 , H01L29/161 , H01L23/535 , H01L29/49 , H01L29/78 , H01L29/08 , H01L29/165
CPC分类号： H01L23/535 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/41791 , H01L29/4966 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： Provided is a semiconductor device having first and second gate electrodes. The semiconductor device includes a substrate, an active region extending in a first direction on the substrate, a first gate electrode crossing the active region and extending in a second direction, and a second gate electrode extending in the second direction on the first gate electrode, wherein the first gate electrode has a first width in the first direction, and wherein the second gate electrode has a second width in the first direction, the second width being less than the first width.
摘要翻译：提供了具有第一和第二栅电极的半导体器件。半导体器件包括衬底，在衬底上沿第一方向延伸的有源区，与有源区交叉并沿第二方向延伸的第一栅极，以及在第一栅电极上沿第二方向延伸的第二栅电极，其中所述第一栅极具有在所述第一方向上的第一宽度，并且其中所述第二栅极具有在所述第一方向上的第二宽度，所述第二宽度小于所述第一宽度。

6. 发明授权

US07307335B2 Semiconductor device having MOS varactor and methods for fabricating the same 有权
标题翻译：具有MOS变容二极管的半导体器件及其制造方法
公开(公告)号：US07307335B2
公开(公告)日：2007-12-11
申请号：US11048715
申请日：2005-02-03
申请人： Dae-Hyun Kim , Han-Su Oh
发明人： Dae-Hyun Kim , Han-Su Oh
IPC分类号： H01L29/00 , H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L27/0808 , H01L27/0811 , H01L29/93 , H01L29/94
摘要： A semiconductor device with having a MOS varactor and methods of fabricating the same are disclosed. The MOS varactor includes a metal gate electrode, an active semiconductor plate interposed between the metal gate electrode and the semiconductor substrate, and a capacitor dielectric layer interposed between the metal gate electrode and the active semiconductor plate. Further, a lower insulating layer insulates the MOS varactor from the semiconductor substrate. According to the present invention, a metal gate electrode is used to reduce poly depletion, thereby increasing a tuning range of the varactor, and to manufacture a reliable metal resistor without the need of an additional photomask.
摘要翻译：公开了具有MOS可变电抗器的半导体器件及其制造方法。 MOS变容二极管包括金属栅极电极，介于金属栅电极和半导体衬底之间的有源半导体板以及置于金属栅电极和有源半导体板之间的电容器介电层。此外，下绝缘层使MOS变容二极管与半导体衬底绝缘。根据本发明，使用金属栅电极来减少多余的耗尽，从而增加变容二极管的调谐范围，并且制造可靠的金属电阻器，而不需要额外的光掩模。

7. 发明授权

US09576959B1 Semiconductor device having first and second gate electrodes and method of manufacturing the same 有权
标题翻译：具有第一和第二栅电极的半导体器件及其制造方法
公开(公告)号：US09576959B1
公开(公告)日：2017-02-21
申请号：US15010327
申请日：2016-01-29
申请人： Yaoqi Dong , Mun Hyeon Kim , Keun Hwi Cho , Shigenobu Maeda , Han Su Oh
发明人： Yaoqi Dong , Mun Hyeon Kim , Keun Hwi Cho , Shigenobu Maeda , Han Su Oh
IPC分类号： H01L29/94 , H01L31/113 , H01L21/00 , H01L21/8238 , H01L27/092 , H01L29/08 , H01L29/161 , H01L29/165 , H01L29/49 , H01L29/78 , H01L23/535
CPC分类号： H01L23/535 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/41791 , H01L29/4966 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： Provided is a semiconductor device having first and second gate electrodes. The semiconductor device includes a substrate, an active region extending in a first direction on the substrate, a first gate electrode crossing the active region and extending in a second direction, and a second gate electrode extending in the second direction on the first gate electrode, wherein the first gate electrode has a first width in the first direction, and wherein the second gate electrode has a second width in the first direction, the second width being less than the first width.
摘要翻译：提供了具有第一和第二栅电极的半导体器件。半导体器件包括衬底，在衬底上沿第一方向延伸的有源区，与有源区交叉并沿第二方向延伸的第一栅极，以及在第一栅电极上沿第二方向延伸的第二栅电极，其中所述第一栅极具有在所述第一方向上的第一宽度，并且其中所述第二栅极具有在所述第一方向上的第二宽度，所述第二宽度小于所述第一宽度。

8. 发明申请

US20050179113A1 Semiconductor device having MOS varactor and methods for fabricating the same 有权
标题翻译：具有MOS变容二极管的半导体器件及其制造方法
公开(公告)号：US20050179113A1
公开(公告)日：2005-08-18
申请号：US11048715
申请日：2005-02-03
申请人： Dae-Hyun Kim , Han-Su Oh
发明人： Dae-Hyun Kim , Han-Su Oh
IPC分类号： H01L27/04 , H01L27/08 , H01L27/108 , H01L29/93 , H01L29/94
CPC分类号： H01L27/0808 , H01L27/0811 , H01L29/93 , H01L29/94
摘要： A semiconductor device with having a MOS varactor and methods of fabricating the same are disclosed. The MOS varactor includes a metal gate electrode, an active semiconductor plate interposed between the metal gate electrode and the semiconductor substrate, and a capacitor dielectric layer interposed between the metal gate electrode and the active semiconductor plate. Further, a lower insulating layer insulates the MOS varactor from the semiconductor substrate. According to the present invention, a metal gate electrode is used to reduce poly depletion, thereby increasing a tuning range of the varactor, and to manufacture a reliable metal resistor without the need of an additional photomask.
摘要翻译：公开了具有MOS可变电抗器的半导体器件及其制造方法。 MOS变容二极管包括金属栅极电极，介于金属栅电极和半导体衬底之间的有源半导体板以及置于金属栅电极和有源半导体板之间的电容器介电层。此外，下绝缘层使MOS变容二极管与半导体衬底绝缘。根据本发明，使用金属栅电极来减少多余的耗尽，从而增加变容二极管的调谐范围，并且制造可靠的金属电阻器，而不需要额外的光掩模。

9. 发明授权

US06613633B2 Method for manufacturing a high power semiconductor device having a field plate extendedly disposed on a gate 有权
标题翻译：用于制造具有扩展地设置在栅极上的场板的大功率半导体器件的制造方法
公开(公告)号：US06613633B2
公开(公告)日：2003-09-02
申请号：US10207996
申请日：2002-07-31
申请人： Han-Su Oh
发明人： Han-Su Oh
IPC分类号： H01L21336
CPC分类号： H01L29/402 , H01L29/0847 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A method to fabricate a high voltage transistor of a smart power device is discussed. The method includes forming a well of first conductivity in a substrate of second conductivity; forming a drift layer of the second conductivity in the well; forming a source region of the second conductivity in the well between a substrate/well junction and a well/drift layer junction; forming a drain region of the second conductivity in the drift layer, the drain region having relatively higher concentration of dopants relative to the drift layer; and forming a first field oxide layer on the drift layer such that the first field oxide layer is spaced apart from the drain region.
摘要翻译：讨论了制造智能功率器件的高压晶体管的方法。该方法包括在第二导电性基板中形成第一导电性的阱; 在井中形成第二导电性的漂移层; 在衬底/阱结与阱/漂移层结之间的阱中形成第二导电性的源极区; 在所述漂移层中形成所述第二导电性的漏极区，所述漏极区相对于所述漂移层具有相对较高的掺杂剂浓度; 以及在所述漂移层上形成第一场氧化物层，使得所述第一场氧化物层与所述漏极区间隔开。

10. 发明授权

US5736765A EEPROM cell having improved topology and reduced leakage current 失效
公开(公告)号：US5736765A
公开(公告)日：1998-04-07
申请号：US451415
申请日：1995-05-26
申请人： Han Su Oh , Jang Han Kim
发明人： Han Su Oh , Jang Han Kim
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L29/66825 , H01L29/42336 , H01L29/7883
摘要： An EEPROM cell of reduced leakage current during erasure and improved cell topology includes a first conductivity type substrate having a channel region, a trench formed in the channel region of the substrate, first spacers formed on opposed sidewalls of the trench, and a gate oxide film formed at the bottom of the trench between the first spacers. Second conductivity type source/drain regions are formed in the substrate at opposite side of the trench. A tunneling oxide film is further provided on the substrate overlying the drain region and proximate the trench. An insulation film is provided over the entire substrate surface except the trench and the tunneling oxide film. In addition, a floating gate is formed on the insulation film over the source and drain regions, as well as the gate oxide film at the trench bottom. Second spacers are provided on the insulation film at opposed side surfaces of the floating gate. A dielectric film is then provided on the surface of the floating gate and the second spacers, and a control gate is formed on the dielectric film.

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