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1. 发明授权

US6009448A Pipelined parallel-serial architecture for a modified least mean square adaptive filter 失效
标题翻译：用于修改的最小均方自适应滤波器的流水线并行串行架构
公开(公告)号：US6009448A
公开(公告)日：1999-12-28
申请号：US912591
申请日：1997-08-18
申请人： Her-Ming Jong , Gwo-Sheng Huang , Wen-Kuang Su , Chao-Hui Hsu
发明人： Her-Ming Jong , Gwo-Sheng Huang , Wen-Kuang Su , Chao-Hui Hsu
IPC分类号： G06F17/15 , H03H21/00 , G06F17/10
CPC分类号： H03H21/0012
摘要： A modified least mean squares adaptive filter method and apparatus is disclosed. The filter coefficients used to perform the FIR multiplications in a least mean squares adaptive filter are time dependent upon a time index. Each tap of the FIR section utilizes a coefficient at a different time index. This allows an implementation in hardware that is modular and easy for implementation in VLSI technologies. In addition, an improve multiplier and accumulator is disclosed for use in implementing the improved least squares adaptive filter.
摘要翻译：公开了一种改进的最小均方自适应滤波方法和装置。用于在最小均方自适应滤波器中执行FIR乘法的滤波器系数取决于时间指数。 FIR部分的每个抽头利用不同时间索引的系数。这允许在硬件中实现模块化并且易于在VLSI技术中实现。另外，公开了一种用于实现改进的最小二乘自适应滤波器的改进乘法器和累加器。

2. 发明授权

US5636339A Circuit structure and system configuration for implementing pseudo four-point interpolation 失效
标题翻译：用于实现伪四点插值的电路结构和系统配置
公开(公告)号：US5636339A
公开(公告)日：1997-06-03
申请号：US209969
申请日：1994-03-14
申请人： Gwo-Sheng Huang , Yee-Lu Zhaog
发明人： Gwo-Sheng Huang , Yee-Lu Zhaog
IPC分类号： G06T3/40 , G06T1/00
CPC分类号： G06T3/4007
摘要： The present invention discloses a data processing module for generating an interpolated output from four sampled input data. The data processing module includes an input means, i.e., a memory module, for receiving the four sampled input data. The data processing module further includes a pseudo four-point interpolation (PFPI) module for receiving a ratio value p and for generating the interpolated output by utilizing a novel pseudo four-point interpolation algorithm as represented by an Equation (6).
摘要翻译：本发明公开了一种用于从四个采样输入数据产生内插输出的数据处理模块。数据处理模块包括用于接收四个采样输入数据的输入装置，即存储器模块。数据处理模块还包括用于接收比值p并用于通过利用由等式（6）表示的新型伪四点插值算法来生成内插输出的伪四点插值（PFPI）模块。

3. 发明授权

US6035319A Parallel-serial multiplier and accumulator 有权
标题翻译：并行串行乘法器和累加器
公开(公告)号：US6035319A
公开(公告)日：2000-03-07
申请号：US146767
申请日：1998-09-03
申请人： Her-Ming Jong , Gwo-Sheng Huang , Wen-Kuang Su , Chao-Hui Hsu
发明人： Her-Ming Jong , Gwo-Sheng Huang , Wen-Kuang Su , Chao-Hui Hsu
IPC分类号： G06F17/15 , H03H21/00 , G06F7/52 , G06F7/38
CPC分类号： H03H21/0012
摘要： An improved parallel-serial multiplier and accumulator for multiplying a digital multiplicand and a multiplier resulting in a product that is added to an accumulator input. The parallel-serial multiplier and accumulator includes a parallel-serial multiplier and a digit serial adder. The parallel-serial multiplier includes a recoder for receiving the digital multiplier and outputting an ordered sequence of recoded words, a partial product generator for generating partial products that are dependent upon the digital multiplicand and upon each of the ordered sequence of recoded words, and an adder for adding the partial products to provide the product. The adder outputs a digit serial word that contains the least significant bits of an intermediate sum of the partial products as the partial products are being added. The digit serial adder includes a carry save adder that receives the product and the accumulator input to produce the output sum.
摘要翻译：一个改进的并行串行乘法器和累加器，用于将数字乘法器和乘法器相乘，产生加到累加器输入端的乘积。并行串行乘法器和累加器包括并行串行乘法器和数字串行加法器。并行串行乘法器包括用于接收数字乘法器并输出有序序列的重新编码字的再编码器，用于产生取决于数字被乘数的部分乘积的部分乘积发生器，以及依赖于重新编码的字的每个有序序列，加法器，用于添加部分产品以提供产品。加法器输出一个数字串行字，该数字串行字包含部分乘积的中间和的最低有效位，因为部分乘积被添加。数字串行加法器包括进位存储加法器，其接收乘积和累加器输入以产生输出和。

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