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1. 发明申请

US20080313392A1 Data controlled power supply apparatus 有权
公开(公告)号：US20080313392A1
公开(公告)日：2008-12-18
申请号：US12222290
申请日：2008-08-06
申请人： Dumitru Cioaca
发明人： Dumitru Cioaca
IPC分类号： G06F12/02 , G06F1/26
CPC分类号： G11C16/30 , G06F1/26 , G06F1/28
摘要： A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit.

2. 发明授权

US07240147B2 Memory decoder and data bus for burst page read 有权
标题翻译：存储器解码器和数据总线用于突发页面读取
公开(公告)号：US07240147B2
公开(公告)日：2007-07-03
申请号：US11416583
申请日：2006-05-03
申请人： Dumitru Cioaca
发明人： Dumitru Cioaca
IPC分类号： G06F12/06 , G06F12/00 , G11C16/06
CPC分类号： G11C7/103 , G11C16/26
摘要： Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page before the currently latched values have been read out. A specialized decoder and a latch control circuit allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or in multiplexing the sense amplifiers. The design allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or multiplexing the sense amplifiers to sense a following set of data bit lines.
摘要翻译：描述了使用减少数量的读出放大器来感测所选列页面的数据位的存储器件。读出放大器被多路复用，并且读取的数据值被锁存，允许读出放大器在读出当前锁存的值之前从所选择的列页面中感测下一组数据线。专门的解码器和锁存器控制电路允许在由于重新加载读取锁存器或复用读出放大器而从存储器读取数据时不存在间隙或延迟。该设计允许在从存储器读取数据时由于重新加载读取锁存器或复用读出放大器以感测下一组数据位线而不存在间隙或延迟。

3. 发明授权

US06765376B2 Voltage converter system and method having a stable output voltage 有权
标题翻译：电压转换器系统和方法具有稳定的输出电压
公开(公告)号：US06765376B2
公开(公告)日：2004-07-20
申请号：US10388051
申请日：2003-03-12
申请人： Christophe J. Chevallier , Dumitru Cioaca
发明人： Christophe J. Chevallier , Dumitru Cioaca
IPC分类号： G05F140
CPC分类号： G05F1/465
摘要： An apparatus and method for compensating for a decreasing internal voltage that is generated from a higher external voltage. In response to the internal voltage decreasing in excess of a voltage margin, the amount by which the higher external voltage is reduced in generating the internal voltage is adjusted to raise the internal voltage.
摘要翻译：一种用于补偿由较高外部电压产生的内部电压降低的装置和方法。响应于内部电压降低超过电压余量，调节产生内部电压时外部电压越高的量，以提高内部电压。

4. 发明授权

US06738298B1 Automatic reference voltage regulation in a memory device 有权
公开(公告)号：US06738298B1
公开(公告)日：2004-05-18
申请号：US10298830
申请日：2002-11-18
申请人： Dumitru Cioaca , Christophe Chevallier , Al Vahidimowlavi , Frankie Fariborz Roohparvar
发明人： Dumitru Cioaca , Christophe Chevallier , Al Vahidimowlavi , Frankie Fariborz Roohparvar
IPC分类号： G11C1604
CPC分类号： G11C29/021 , G11C5/147 , G11C7/14 , G11C29/02 , G11C29/028 , G11C2029/5004
摘要： A transition of an external enable signal generates a reset pulse to a counter to set the counter into a known state. The counter, clocked by the external clock signal, generates a clock signal that is decoded by a fuse decoder circuit. The fuse decoder circuit outputs a selection signal to a trim circuit. The trim circuit produces a voltage selection signal, such as a resistance value, that is indicated by the selection signal for use by an internal reference voltage generation circuit. The output of the internal reference voltage generation circuit is compared to the external reference voltage. The counter circuit continues counting until the internal reference voltage is equal to or greater than the external reference voltage. The counter is disabled and the final count that produced the proper internal reference voltage is stored in non-volatile memory cells for future use.

5. 发明授权

US09165666B2 Charge pump apparatus, a memory integrated circuit and methods of power supply 有权
标题翻译：电荷泵装置，存储器集成电路和电源方法
公开(公告)号：US09165666B2
公开(公告)日：2015-10-20
申请号：US13315385
申请日：2011-12-09
申请人： Dumitru Cioaca
发明人： Dumitru Cioaca
IPC分类号： G06F1/26 , G11C16/30 , G06F1/28
CPC分类号： G11C16/30 , G06F1/26 , G06F1/28
摘要： A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit. A charge pump apparatus and a memory integrated circuit are also described.
摘要翻译：根据数据总线上的数字数据信号的状态，电源和控制电源的方法，其中电源的功率容量或多或少是激活的。电源具有检测数据总线上存在的“零”位的数量的控制电路，并且响应地激活多个电源电路中的一个或多个，例如电荷泵电路。电荷泵电路的输出相互连接到适于编程闪存电路的存储单元的驱动器。还描述了电荷泵装置和存储器集成电路。

6. 发明授权

US07149143B2 Decoder for memory data bus 有权
公开(公告)号：US07149143B2
公开(公告)日：2006-12-12
申请号：US11305777
申请日：2005-12-16
申请人： Dumitru Cioaca
发明人： Dumitru Cioaca
IPC分类号： G11C8/00
CPC分类号： G11C7/103 , G11C16/26
摘要： Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page before the currently latched values have been read out. A specialized decoder and a latch control circuit allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or in multiplexing the sense amplifiers. The design allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or multiplexing the sense amplifiers to sense a following set of data bit lines.

7. 发明授权

US07093062B2 Flash memory data bus for synchronous burst read page 有权
公开(公告)号：US07093062B2
公开(公告)日：2006-08-15
申请号：US10411422
申请日：2003-04-10
申请人： Dumitru Cioaca
发明人： Dumitru Cioaca
IPC分类号： G06F12/00
CPC分类号： G11C7/103 , G11C16/26
摘要： Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page before the currently latched values have been read out. A specialized decoder and a latch control circuit allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or in multiplexing the sense amplifiers. The design allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or multiplexing the sense amplifiers to sense a following set of data bit lines.

8. 发明申请

US20060098522A1 Decoder for memory data bus 有权
公开(公告)号：US20060098522A1
公开(公告)日：2006-05-11
申请号：US11305777
申请日：2005-12-16
申请人： Dumitru Cioaca
发明人： Dumitru Cioaca
IPC分类号： G11C8/00
CPC分类号： G11C7/103 , G11C16/26
摘要： Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page before the currently latched values have been read out. A specialized decoder and a latch control circuit allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or in multiplexing the sense amplifiers. The design allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or multiplexing the sense amplifiers to sense a following set of data bit lines.

9. 发明授权

US06900625B2 Voltage converter system and method having a stable output voltage 有权
标题翻译：电压转换器系统和方法具有稳定的输出电压
公开(公告)号：US06900625B2
公开(公告)日：2005-05-31
申请号：US10388058
申请日：2003-03-12
申请人： Christophe J. Chevallier , Dumitru Cioaca
发明人： Christophe J. Chevallier , Dumitru Cioaca
IPC分类号： G05F1/46 , G08B21/00 , G05F1/44
CPC分类号： G05F1/465
摘要： An apparatus and method for compensating for a decreasing internal voltage that is generated from a higher external voltage. In response to the internal voltage decreasing in excess of a voltage margin, the amount by which the higher external voltage is reduced in generating the internal voltage is adjusted to raise the internal voltage.
摘要翻译：一种用于补偿由较高外部电压产生的内部电压降低的装置和方法。响应于内部电压降低超过电压余量，调节产生内部电压时外部电压越高的量，以提高内部电压。

10. 发明授权

US06687165B1 Temperature-compensated output buffer circuit 有权
标题翻译：温度补偿输出缓冲电路
公开(公告)号：US06687165B1
公开(公告)日：2004-02-03
申请号：US10329839
申请日：2002-12-26
申请人： Dumitru Cioaca
发明人： Dumitru Cioaca
IPC分类号： G11C700
CPC分类号： G11C7/04 , G05F3/245 , G11C7/1051 , G11C7/1057 , H03K19/00384 , H03K19/018528
摘要： An output buffer circuit that compensates for ambient temperature changes facilitates more consistent current drive capacity across a range of ambient temperatures. The number of output buffer stages utilized to generate the data output signal is varied in response to changes in ambient temperature.
摘要翻译：补偿环境温度变化的输出缓冲电路有助于在一定范围的环境温度下实现更一致的电流驱动能力。用于产生数据输出信号的输出缓冲器级数随着环境温度的变化而变化。

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