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1. 发明授权

US06795944B2 Testing regularly structured logic circuits in integrated circuit devices 失效
标题翻译：在集成电路设备中测试定期结构化的逻辑电路
公开(公告)号：US06795944B2
公开(公告)日：2004-09-21
申请号：US09853106
申请日：2001-05-10
申请人： Carl F. Barnhart
发明人： Carl F. Barnhart
IPC分类号： G01R313177
CPC分类号： G01R31/318563 , G11C2029/0401
摘要： The test generation software takes advantage of the regularity of the structure without introducing significant changes to the test pattern generation software or to the manufacturing test tools. In this manner, the number of test patterns, the pattern data volume, and the length of the scan chains used for testing the imbedded repetitive structures is substantially reduced. The imbedded repetitive structures are tested by structuring and connecting the scan chain segments of the repeated structures in a way that permits identical test stimuli to be loaded into each copy of the repeated structure. A multiple input signature register or other such equivalent data compressing means provide the necessary data compression for reducing the volume of the test results that can be observed during scan by the tester to detect the presence of any fault that was observed.
摘要翻译：测试生成软件利用结构的规则性，而不会对测试模式生成软件或制造测试工具引入重大变化。以这种方式，用于测试嵌入的重复结构的测试图案的数量，图案数据量和扫描链的长度显着减少。通过将重复结构的扫描链段以允许相同的测试刺激加载到重复结构的每个拷贝的方式来测试嵌入的重复结构。多输入签名寄存器或其他这样的等效数据压缩装置提供必要的数据压缩，以减少测试者在扫描期间可以观察到的测试结果的体积，以检测观察到的任何故障的存在。

2. 发明授权

US07305600B2 Partial good integrated circuit and method of testing same 有权
标题翻译：部分良好的集成电路及其测试方法
公开(公告)号：US07305600B2
公开(公告)日：2007-12-04
申请号：US10651874
申请日：2003-08-29
申请人： Leonard O. Farnsworth, III , Michael Z. Felske , Pamela S. Gillis , Benjamin P. Lynch , Michael R. Ouellette , Thomas St.Pierre , Tad J. Wilder , Carl F. Barnhart
发明人： Leonard O. Farnsworth, III , Michael Z. Felske , Pamela S. Gillis , Benjamin P. Lynch , Michael R. Ouellette , Thomas St.Pierre , Tad J. Wilder , Carl F. Barnhart
IPC分类号： G01R31/28
CPC分类号： G01R31/318558 , G01R31/318505 , G01R31/318516 , G11C2029/1208 , G11C2029/3202
摘要： An integrated circuit, including: a multiplicity of macro-circuits, each macro-circuit having the same function; a fuse bank containing a multiplicity of fuses, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.
摘要翻译：一种集成电路，包括：多个宏电路，每个宏电路具有相同的功能; 包含多个保险丝的保险丝库，保险丝的状态存储测试数据，至少指示哪些宏电路测试失败; 以及用于防止在集成电路运行期间利用故障宏电路的装置和产生部分良好集成电路的方法，所述方法包括：提供集成电路，其具有以一组或多组布置的多个宏电路，每个宏具有相同功能的电路和包含保险丝的保险丝库; 在保险丝编程操作之前测试每个宏电路; 对保险丝组中的熔丝进行编程，以便存储指示测试步骤中至少哪些宏电路失败的数据; 并且基于存储在熔丝库中的数据，防止在集成的操作期间利用每个故障的宏电路。

3. 发明授权

US06804803B2 Method for testing integrated logic circuits 有权
标题翻译：集成逻辑电路测试方法
公开(公告)号：US06804803B2
公开(公告)日：2004-10-12
申请号：US09681438
申请日：2001-04-05
申请人： Carl F. Barnhart , Robert W. Bassett , Brion L. Keller , David E. Lackey , Mark R. Taylor , Donald L. Wheater
发明人： Carl F. Barnhart , Robert W. Bassett , Brion L. Keller , David E. Lackey , Mark R. Taylor , Donald L. Wheater
IPC分类号： G06F1100
CPC分类号： G06F11/263
摘要： A method of testing a circuit having multiple elements is disclosed. A plurality of faults representing the elements of the circuit for testing said circuit is created. The faults are grouped based on common attributes of the faults. A test pattern for each group of faults is created. Finally, the circuit is tested using test patterns for each group of faults.
摘要翻译：公开了一种测试具有多个元件的电路的方法。创建表示用于测试所述电路的电路元件的多个故障。故障根据故障的常见属性进行分组。创建每组故障的测试模式。最后，使用每组故障的测试模式对电路进行测试。

4. 发明授权

US07478301B2 Partial good integrated circuit and method of testing same 失效
标题翻译：部分良好的集成电路及其测试方法
公开(公告)号：US07478301B2
公开(公告)日：2009-01-13
申请号：US12114198
申请日：2008-05-02
申请人： Leonard O. Farnsworth, III , Michael Z. Felske , Pamela S. Gillis , Benjamin P. Lynch , Michael R. Ouellette , Thomas St. Pierre , Tad J. Wilder , Carl F. Barnhart
发明人： Leonard O. Farnsworth, III , Michael Z. Felske , Pamela S. Gillis , Benjamin P. Lynch , Michael R. Ouellette , Thomas St. Pierre , Tad J. Wilder , Carl F. Barnhart
IPC分类号： G01R31/28
CPC分类号： G01R31/318558 , G01R31/318505 , G01R31/318516 , G11C2029/1208 , G11C2029/3202
摘要： An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.
摘要翻译：集成电路的测试和维修的集成电路和方法。集成电路包括：具有相同功能的多个宏电路; 保险丝库，保险丝的状态存储测试数据，至少指示哪些宏观电路未通过测试; 以及用于防止在集成电路运行期间利用故障宏电路的装置和产生部分良好集成电路的方法，所述方法包括：提供集成电路，其具有以一组或多组布置的多个宏电路，每个宏具有相同功能的电路和包含保险丝的保险丝库; 在保险丝编程操作之前测试每个宏电路; 对保险丝组中的熔丝进行编程，以便存储指示测试步骤中至少哪些宏电路失败的数据; 并且基于存储在熔丝库中的数据，防止在集成的操作期间利用每个故障的宏电路。

5. 发明授权

US07434129B2 Partial good integrated circuit and method of testing same 失效
标题翻译：部分良好的集成电路及其测试方法
公开(公告)号：US07434129B2
公开(公告)日：2008-10-07
申请号：US11859834
申请日：2007-09-24
申请人： Leonard O. Farnsworth, III , Michael Z. Felske , Pamela S. Gillia , Benjamin P. Lynch , Michael R. Ouellette , Thomas St. Pierre , Tad J. Wilder , Carl F. Barnhart
发明人： Leonard O. Farnsworth, III , Michael Z. Felske , Pamela S. Gillia , Benjamin P. Lynch , Michael R. Ouellette , Thomas St. Pierre , Tad J. Wilder , Carl F. Barnhart
IPC分类号： G01R31/28
CPC分类号： G01R31/318558 , G01R31/318505 , G01R31/318516 , G11C2029/1208 , G11C2029/3202
摘要： An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.
摘要翻译：集成电路的测试和修复的集成电路和方法。集成电路包括：具有相同功能的多个宏电路; 保险丝库，保险丝的状态存储测试数据，至少指示哪些宏观电路未通过测试; 以及用于防止在集成电路运行期间利用故障宏电路的装置和产生部分良好集成电路的方法，所述方法包括：提供集成电路，其具有以一组或多组布置的多个宏电路，每个宏具有相同功能的电路和包含保险丝的保险丝库; 在保险丝编程操作之前测试每个宏电路; 对保险丝组中的熔丝进行编程，以便存储指示测试步骤中至少哪些宏电路失败的数据; 并且基于存储在熔丝库中的数据，防止在集成的操作期间利用每个故障的宏电路。

6. 发明申请

US20080209289A1 PARTIAL GOOD INTEGRATED CIRCUIT AND METHOD OF TESTING SAME 失效
标题翻译：部分良好集成电路及其测试方法
公开(公告)号：US20080209289A1
公开(公告)日：2008-08-28
申请号：US12114198
申请日：2008-05-02
申请人： Leonard O. Farnsworth , Michael Z. Felske , Pamela S. Gillis , Benjamin P. Lynch , Michael R. Ouellette , Thomas St. Pierre , Tad J. Wilder , Carl F. Barnhart
发明人： Leonard O. Farnsworth , Michael Z. Felske , Pamela S. Gillis , Benjamin P. Lynch , Michael R. Ouellette , Thomas St. Pierre , Tad J. Wilder , Carl F. Barnhart
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318558 , G01R31/318505 , G01R31/318516 , G11C2029/1208 , G11C2029/3202
摘要： An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.
摘要翻译：集成电路的测试和修复的集成电路和方法。集成电路包括：具有相同功能的多个宏电路; 保险丝库，保险丝的状态存储测试数据，至少指示哪些宏观电路未通过测试; 以及用于防止在集成电路运行期间利用故障宏电路的装置和产生部分良好集成电路的方法，所述方法包括：提供集成电路，其具有以一组或多组布置的多个宏电路，每个宏具有相同功能的电路和包含保险丝的保险丝库; 在保险丝编程操作之前测试每个宏电路; 对保险丝组中的保险丝进行编程，以便存储指示测试步骤中至少哪些宏电路失败的数据; 并且基于存储在熔丝库中的数据，防止在集成的操作期间利用每个故障的宏电路。

7. 发明授权

US4205303A Performing arithmetic using indirect digital-to-analog conversion 失效
标题翻译：使用间接数模转换执行算术
公开(公告)号：US4205303A
公开(公告)日：1980-05-27
申请号：US892244
申请日：1978-03-31
申请人： Carl F. Barnhart
发明人： Carl F. Barnhart
IPC分类号： H03M1/66 , G06J1/00 , H03M1/00 , H03K13/02
CPC分类号： G06J1/00 , H03M1/827
摘要： Circuitry and method for adding, subtracting, multiplying and/or dividing a plurality of multi-bit, arbitrarily signed, changeable, coded digital input signals representing numerical values to convert said signals into a single analog output signal of predetermined amplitude having a fixed period but a duty cycle that is proportional to the algebraic sum or product or quotient of said input signals. This is accomplished using indirect digital-to-analog conversion.
摘要翻译：用于将表示数值的多个多位，任意签名的，可变化的编码数字输入信号相加，减法，乘法和/或分频以将所述信号转换成具有固定周期的预定幅度的单个模拟输出信号的电路和方法，与所述输入信号的代数和或乘积成比例的占空比。这是使用间接数模转换完成的。

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