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    • 7. 发明授权
    • Adapter for the connection to a clear-channel telecommunication network
    • 用于连接到清晰通道电信网络的适配器
    • US5519737A
    • 1996-05-21
    • US48598
    • 1993-04-19
    • Alain BrunJean-marc CazaentreHenri GiulianoPatrick Sicsic
    • Alain BrunJean-marc CazaentreHenri GiulianoPatrick Sicsic
    • H04L7/00H04J3/06H04L7/033H04L7/10H04M3/00H03D3/24
    • H04L7/10H04J3/0685H04L7/0331
    • An adapter having a line interface circuit for providing an analog attachment to a network (100). The line interface circuit is provided with a reset input for beginning a resynchronization of the timing of the adapter. The adapter further includes a Digital Phase-locked Loop device DPLL (203) driven by a master clock (306) which provides the timing and synchronization signals to the line interface circuits (201). The DPLL (203) divides a master clock down to an internal INT clock (309), a phase comparator (303) compares the INT clock with a reference signal (302) which is synchronized with the receive clock (202) extracted from the line by line interface (201). The phase comparison process operates with a Correction Signal (CS) which has a window centered around the falling edge of the INT clock. A frequency correction is initiated when the reference clock falls outside of the correction window and is achieved by inserting or suppressing a master clock pulse at this time. The adapter further includes means for resetting the line interface circuits and the DPLL at the power-on of the adapter, such that the frequency correction apparatus of the adapter causes two adapters attached at separate ends of a transmission medium to evolve toward stable timing states with respect to each other.
    • 具有用于向网络(100)提供模拟附件的线路接口电路的适配器。 线路接口电路设置有用于开始适配器的定时的再同步的复位输入。 适配器还包括由主时钟(306)驱动的数字锁相环装置DPLL(203),其将时序和同步信号提供给线路接口电路(201)。 DPLL(203)将主时钟下降到内部INT时钟(309),相位比较器(303)将INT时钟与与从线提取的接收时钟(202)同步的参考信号(302)进行比较 (201)。 相位比较过程使用具有以INT时钟的下降沿为中心的窗口的校正信号(CS)进行操作。 当参考时钟落在校正窗口之外时,开始频率校正,并通过插入或抑制此时的主时钟脉冲来实现。 适配器还包括用于在适配器的电源接通时复位线路接口电路和DPLL的装置,使得适配器的频率校正装置使得连接在传输介质的分离端处的两个适配器朝着稳定的定时状态演变, 相互尊重