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1. 发明申请

US20090236689A1 INTEGRATED PASSIVE DEVICE AND METHOD WITH LOW COST SUBSTRATE 审中-公开
标题翻译：集成无源器件和低成本基板的方法
公开(公告)号：US20090236689A1
公开(公告)日：2009-09-24
申请号：US12054105
申请日：2008-03-24
申请人： Terry K. Daly , Keri L. Costello , James G. Cotronakis , Jason R. Fender , Jeff S. Hughes , Agni Mitra , Adolfo C. Reyes
发明人： Terry K. Daly , Keri L. Costello , James G. Cotronakis , Jason R. Fender , Jeff S. Hughes , Agni Mitra , Adolfo C. Reyes
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L27/016 , H01L23/5227 , H01L23/5228 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device (72), is provided. An insulating initial dielectric layer (32) comprising charge trapping films of, for example, aluminum nitride or silicon nitride or silicon oxide or a combination thereof, is formed over a silicon substrate (20). At least one passive electronic component (62) is formed over the initial dielectric layer (32). In an embodiment where silicon nitride or oxide is used in the initial dielectric layer (32) in contact with the silicon substrate (20), it is desirable to pre-treat the silicon surface (22) by exposing it to a surface damage causing treatment (e.g. an argon plasma) prior to depositing the initial dielectric layer, to assist in providing carrier depletion near the silicon surface around zero bias. RF loss in integrated passive devices using such silicon substrates is equal or lower than that obtained with GaAs substrates.
摘要翻译：根据本发明的一个方面，提供了一种形成微电子组件的方法，诸如集成无源器件（72）。在硅衬底（20）上形成包括例如氮化铝或氮化硅或氧化硅或其组合的电荷捕获膜的绝缘初始介电层（32）。在初始介电层（32）上形成至少一个无源电子部件（62）。在与硅衬底（20）接触的初始电介质层（32）中使用氮化硅或氧化物的实施例中，期望通过将硅表面（22）暴露于导致处理的表面损伤来预处理硅表面（22）（例如氩等离子体），以便辅助在靠近零偏压的硅表面附近提供载流子耗尽。使用这种硅衬底的集成无源器件中的RF损耗等于或低于用GaAs衬底获得的RF损耗。

2. 发明申请

US20070132029A1 ESD protection for passive integrated devices 有权
标题翻译：无源集成器件的ESD保护
公开(公告)号：US20070132029A1
公开(公告)日：2007-06-14
申请号：US11300710
申请日：2005-12-14
申请人： Agni Mitra , Darrell Hill , Karthik Rajagopalan , Adolfo Reyes
发明人： Agni Mitra , Darrell Hill , Karthik Rajagopalan , Adolfo Reyes
IPC分类号： H01L23/62
CPC分类号： H01L23/62 , H01L27/0248 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , Y10T29/413 , Y10T29/49204 , H01L2924/00
摘要： Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.
摘要翻译：为集成无源器件（IPD）的ESD保护提供了方法和设备。该装置包括一个或多个IPD，其具有潜在地暴露于ESD瞬变的端子或其他元件，其通过电荷泄漏电阻耦合，其电阻值比在感兴趣的工作频率下的IPD的普通阻抗大得多。当IPD构建在半绝缘基板上时，IPD的各种元件通过间隔开的连接件耦合到基板，使得基板本身提供耦合元件的高价值电阻，但这不是必须的。当应用于IPD RF耦合器时，ESD耐受性提高了70％以上。本发明的布置还可以应用于有源器件和集成电路以及具有导电或绝缘衬底的IPD。

3. 发明授权

US09437693B2 Device having a shield plate dopant region and method of manufacturing same 有权
标题翻译：具有屏蔽板掺杂剂区域的器件及其制造方法
公开(公告)号：US09437693B2
公开(公告)日：2016-09-06
申请号：US14572773
申请日：2014-12-17
申请人： Zihao M. Gao , David C. Burdeaux , Agni Mitra
发明人： Zihao M. Gao , David C. Burdeaux , Agni Mitra
IPC分类号： H01L29/76 , H01L29/40 , H01L29/78 , H01L29/66
CPC分类号： H01L29/7823 , H01L29/0611 , H01L29/0882 , H01L29/1087 , H01L29/1095 , H01L29/167 , H01L29/402 , H01L29/404 , H01L29/4175 , H01L29/66659 , H01L29/66712 , H01L29/7835
摘要： A transistor includes a surface region, a gate, a source dopant region, a drain dopant region, a drift dopant region, a set of electrically conductive shield plates, and a shield plate dopant region. A sidewall of the gate aligns with a drain side boundary of the surface region. The drain dopant region is within the surface region on the drain side. The drift dopant region is within the surface region between the drain side boundary and the drain dopant region. The set of electrically conductive shield plates includes a first shield plate overlying the drift dopant region. The shield plate dopant region is within the drift dopant region and underlies the set of shield plates.
摘要翻译：晶体管包括表面区域，栅极，源极掺杂区域，漏极掺杂剂区域，漂移掺杂区域，一组导电屏蔽板以及屏蔽板掺杂区域。栅极的侧壁与表面区域的漏极边界对准。漏极掺杂剂区域在漏极侧的表面区域内。漂移掺杂剂区域在漏极侧边界和漏极掺杂剂区域之间的表面区域内。该组导电屏蔽板包括覆盖漂移掺杂剂区域的第一屏蔽板。屏蔽板掺杂剂区域在漂移掺杂区域内并且位于该组屏蔽板之下。

4. 发明申请

US20130146973A1 CUSTOMIZED SHIELD PLATE FOR A FIELD EFFECT TRANSISTOR 有权
标题翻译：用于场效应晶体管的自定义屏蔽板
公开(公告)号：US20130146973A1
公开(公告)日：2013-06-13
申请号：US13324910
申请日：2011-12-13
申请人： Agni Mitra , David C. Burdeaux
发明人： Agni Mitra , David C. Burdeaux
IPC分类号： H01L29/78 , H01L21/31
CPC分类号： H01L29/402 , H01L29/0692 , H01L29/404 , H01L29/4175 , H01L29/66719 , H01L29/7835
摘要： A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications.
摘要翻译：定制的屏蔽板场效应晶体管（FET）包括半导体层，栅极电介质，栅极电极和至少一个定制的屏蔽板。屏蔽板包括覆盖栅电极的一部分，栅极电极侧壁中的一个和与侧壁相邻的基板的一部分的导电层。屏蔽板在其横向边界处限定了定制的屏蔽板边缘。定制的屏蔽板边缘和栅电极的侧壁之间的距离沿侧壁的长度变化。定制的屏蔽板边缘可以形成三角形，弯曲形和其他形状的屏蔽板元件。定制的屏蔽板边缘的配置可以减小所得电容器的面积，从而实现与FET相关联的较低的寄生电容。 FET可以被实现为适合于高功率射频应用的横向漫射MOS（LDMOS）晶体管。

5. 发明申请

US20080108217A1 ESD PROTECTION FOR PASSIVE INTEGRATED DEVICES 有权
标题翻译：被动集成设备的ESD保护
公开(公告)号：US20080108217A1
公开(公告)日：2008-05-08
申请号：US11972475
申请日：2008-01-10
申请人： Agni Mitra , Darrell Hill , Karthik Rajagopalan , Adolfo Reyes
发明人： Agni Mitra , Darrell Hill , Karthik Rajagopalan , Adolfo Reyes
IPC分类号： H01L21/64 , H01L21/28 , H01R43/16
CPC分类号： H01L23/62 , H01L27/0248 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , Y10T29/413 , Y10T29/49204 , H01L2924/00
摘要： Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.
摘要翻译：为集成无源器件（IPD）的ESD保护提供了方法和设备。该装置包括一个或多个IPD，其具有潜在地暴露于ESD瞬变的端子或其他元件，其通过电荷泄漏电阻耦合，其电阻值比在感兴趣的工作频率下的IPD的普通阻抗大得多。当IPD构建在半绝缘基板上时，IPD的各种元件通过间隔开的连接件耦合到基板，使得基板本身提供耦合元件的高价值电阻，但这不是必须的。当应用于IPD RF耦合器时，ESD耐受性提高了70％以上。本发明的布置还可以应用于有源器件和集成电路以及具有导电或绝缘衬底的IPD。

6. 发明申请

US20160181378A1 DEVICE HAVING A SHIELD PLATE DOPANT REGION AND METHOD OF MANUFACTURING SAME 有权
标题翻译：具有屏蔽板区域的装置及其制造方法
公开(公告)号：US20160181378A1
公开(公告)日：2016-06-23
申请号：US14572773
申请日：2014-12-17
申请人： Zihao M. Gao , David C. Burdeaux , Agni Mitra
发明人： Zihao M. Gao , David C. Burdeaux , Agni Mitra
IPC分类号： H01L29/40 , H01L29/66 , H01L29/78
CPC分类号： H01L29/7823 , H01L29/0611 , H01L29/0882 , H01L29/1087 , H01L29/1095 , H01L29/167 , H01L29/402 , H01L29/404 , H01L29/4175 , H01L29/66659 , H01L29/66712 , H01L29/7835
摘要： A transistor includes a surface region, a gate, a source dopant region, a drain dopant region, a drift dopant region, a set of electrically conductive shield plates, and a shield plate dopant region. A sidewall of the gate aligns with a drain side boundary of the surface region. The drain dopant region is within the surface region on the drain side. The drift dopant region is within the surface region between the drain side boundary and the drain dopant region. The set of electrically conductive shield plates includes a first shield plate overlying the drift dopant region. The shield plate dopant region is within the drift dopant region and underlies the set of shield plates.
摘要翻译：晶体管包括表面区域，栅极，源极掺杂区域，漏极掺杂区域，漂移掺杂区域，一组导电屏蔽板以及屏蔽板掺杂区域。栅极的侧壁与表面区域的漏极边界对准。漏极掺杂剂区域在漏极侧的表面区域内。漂移掺杂剂区域在漏极侧边界和漏极掺杂剂区域之间的表面区域内。该组导电屏蔽板包括覆盖漂移掺杂剂区域的第一屏蔽板。屏蔽板掺杂剂区域在漂移掺杂区域内并且位于该组屏蔽板之下。

7. 发明授权

US08680615B2 Customized shield plate for a field effect transistor 有权
标题翻译：用于场效应晶体管的定制屏蔽板
公开(公告)号：US08680615B2
公开(公告)日：2014-03-25
申请号：US13324910
申请日：2011-12-13
申请人： Agni Mitra , David C. Burdeaux
发明人： Agni Mitra , David C. Burdeaux
IPC分类号： H01L29/66
CPC分类号： H01L29/402 , H01L29/0692 , H01L29/404 , H01L29/4175 , H01L29/66719 , H01L29/7835
摘要： A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications.
摘要翻译：定制的屏蔽板场效应晶体管（FET）包括半导体层，栅极电介质，栅极电极和至少一个定制的屏蔽板。屏蔽板包括覆盖栅电极的一部分，栅极电极侧壁中的一个和与侧壁相邻的基板的一部分的导电层。屏蔽板在其横向边界处限定了定制的屏蔽板边缘。定制的屏蔽板边缘和栅电极的侧壁之间的距离沿侧壁的长度变化。定制的屏蔽板边缘可以形成三角形，弯曲形和其他形状的屏蔽板元件。定制的屏蔽板边缘的配置可以减小所得电容器的面积，从而实现与FET相关联的较低的寄生电容。 FET可以被实现为适合于高功率射频应用的横向漫射MOS（LDMOS）晶体管。

8. 发明授权

US07642182B2 ESD protection for passive integrated devices 有权
标题翻译：无源集成器件的ESD保护
公开(公告)号：US07642182B2
公开(公告)日：2010-01-05
申请号：US11972475
申请日：2008-01-10
申请人： Agni Mitra , Darrell G. Hill , Karthik Rajagopalan , Adolfo C. Reyes
发明人： Agni Mitra , Darrell G. Hill , Karthik Rajagopalan , Adolfo C. Reyes
IPC分类号： H01L21/44
CPC分类号： H01L23/62 , H01L27/0248 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , Y10T29/413 , Y10T29/49204 , H01L2924/00
摘要： Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.
摘要翻译：为集成无源器件（IPD）的ESD保护提供了方法和设备。该装置包括一个或多个IPD，其具有潜在地暴露于ESD瞬变的端子或其他元件，其通过电荷泄漏电阻耦合，其电阻值比在感兴趣的工作频率下的IPD的普通阻抗大得多。当IPD构建在半绝缘基板上时，IPD的各种元件通过间隔开的连接件耦合到基板，使得基板本身提供耦合元件的高价值电阻，但这不是必须的。当应用于IPD RF耦合器时，ESD耐受性提高了70％以上。本发明的布置还可以应用于有源器件和集成电路以及具有导电或绝缘衬底的IPD。

9. 发明授权

US07335955B2 ESD protection for passive integrated devices 有权
标题翻译：无源集成器件的ESD保护
公开(公告)号：US07335955B2
公开(公告)日：2008-02-26
申请号：US11300710
申请日：2005-12-14
申请人： Agni Mitra , Darrell G. Hill , Karthik Rajagopalan , Adolfo C. Reyes
发明人： Agni Mitra , Darrell G. Hill , Karthik Rajagopalan , Adolfo C. Reyes
IPC分类号： H01L23/62
CPC分类号： H01L23/62 , H01L27/0248 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , Y10T29/413 , Y10T29/49204 , H01L2924/00
摘要： Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.
摘要翻译：为集成无源器件（IPD）的ESD保护提供了方法和设备。该装置包括一个或多个IPD，其具有潜在地暴露于ESD瞬变的端子或其他元件，其通过电荷泄漏电阻耦合，其电阻值比在感兴趣的工作频率下的IPD的普通阻抗大得多。当IPD构建在半绝缘基板上时，IPD的各种元件通过间隔开的连接件耦合到基板，使得基板本身提供耦合元件的高价值电阻，但这不是必须的。当应用于IPD RF耦合器时，ESD耐受性提高了70％以上。本发明的布置还可以应用于有源器件和集成电路以及具有导电或绝缘衬底的IPD。

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