Embodiments of the present application relate to the technical field of memories, and provide a thin film transistor, a memory and a manufacturing method, and an electronic device, capable of reducing the size of the thin film transistor, improving area utilization, and reduce wiring difficulty. The thin film transistor comprises a gate electrode, a first electrode, a second electrode, a first dielectric layer, a second dielectric layer, and a semiconductor layer. The gate electrode comprises a gate substrate located at the top and a gate electrode column extending from the gate substrate to the bottom; the first electrode is located at the bottom; the second electrode is located between the first electrode and the gate substrate; the first dielectric layer is disposed between the second electrode and the first electrode, and is used for separating the first electrode from the second electrode; the second dielectric layer covers the surface of the gate substrate and the surface of the gate electrode column; the semiconductor layer is disposed along the side surface of the gate electrode column, and the second dielectric layer separates the semiconductor layer from the gate electrode. The first electrode and the second electrode are electrically connected to the semiconductor layer, respectively.