Disclosed are a terminal resistance circuit, a chip, and a chip communication apparatus, which relate to the technical field of semiconductor integrated circuits. The terminal resistance circuit is applied to a high-speed differential I/O pair of a chip. The high-speed differential I/O pair comprises a first interface and a second interface. The terminal resistance circuit comprises two resistance circuits and a control circuit, wherein one end, after the two resistance circuits are connected in series, is electrically connected to the first interface, and the other end, after the two resistance circuits are connected in series, is electrically connected to the second interface; there is a target node on a wire between the two resistance circuits; the two resistance circuits are symmetrically arranged with respect to the target node; and the control circuit is respectively electrically connected to the two resistance circuits and is used for controlling, during a chip powering-on process, the two resistance circuits to be in a cut-off state. According to the present application, the problem that a system works abnormally due to short-circuiting of two I/Os during the chip powering-on process can be avoided, thereby improving the working stability of the chip.