发明申请
WO2020188951A1 FERROELECTRIC LOW POWER 2D MEMORY TRANSISTOR AND FABRICATION METHOD THEREOF
审中-公开
基本信息:
- 专利标题： FERROELECTRIC LOW POWER 2D MEMORY TRANSISTOR AND FABRICATION METHOD THEREOF
- 申请号：PCT/JP2019/051645 申请日：2019-12-23
- 公开(公告)号：WO2020188951A1 公开(公告)日：2020-09-24
- 发明人： TEO, Koon Hoo , SHEN, Pinchun , LIN, Chungwei
- 申请人： MITSUBISHI ELECTRIC CORPORATION
- 申请人地址： 7-3, Marunouchi 2-chome, Chiyoda-ku Tokyo 100-8310 JP
- 专利权人： MITSUBISHI ELECTRIC CORPORATION
- 当前专利权人： MITSUBISHI ELECTRIC CORPORATION
- 当前专利权人地址： 7-3, Marunouchi 2-chome, Chiyoda-ku Tokyo 100-8310 JP
- 代理机构： FUKAMI PATENT OFFICE, P.C.
- 优先权： US16/356,067 20190318
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L29/51 ; H01L29/66 ; H01L29/786
摘要：
Disclosed is a transistor device including a memory cell comprising a gate stack with sidewalls provided over a substrate. The gate stack includes a metal gate layer provided over the substrate. A buffer layer is provided over the metal gate layer, a ferroelectric layer is provided over the buffer layer, and a dielectric layer is provided over the ferroelectric layer. A two-dimensional, 2D, material layer is provided over a portion of a top surface of the dielectric layer. Source and drain regions are provided on separate portions of the top surface of the dielectric layer so as to create a cavity wherein the 2D material layer is located.
IPC结构图谱:
| H | 电学 |
| --H01 | 基本电气元件 |
| ----H01L | 半导体器件；其他类目未包含的电固体器件 |
| ------H01L29/00 | 专门适用于整流、放大、振荡或切换，并具有至少一个电位跃变势垒或表面势垒的半导体器件；具有至少一个电位跃变势垒或表面势垒，例如PN结耗尽层或载流子集结层的电容器或电阻器；半导体本体或其电极的零部件 |
| --------H01L29/02 | .按其半导体本体的特征区分的 |
| ----------H01L29/68 | ..只能通过对一个不通有待整流、放大或切换的电流的电极供给电流或施加电位方可进行控制的 |
| ------------H01L29/70 | ...双极器件 |
| --------------H01L29/762 | ....电荷转移器件 |
| ----------------H01L29/78 | .....由绝缘栅产生场效应的 |