基本信息:
- 专利标题: TEXTURE BREAKING LAYER TO DECOUPLE BOTTOM ELECTRODE FROM PMTJ DEVICE
- 专利标题(中):纹理断层以从PMTJ装置中分离底部电极
- 申请号:PCT/US2016/025709 申请日:2016-04-01
- 公开(公告)号:WO2017171869A1 公开(公告)日:2017-10-05
- 发明人: MAERTZ, Brian , WIEGAND, Christopher, J. , OEULLETTE, Daniel, G. , RAHMAN, MD Tofizur , GOLONZKA, Oleg , BROCKMAN, Justin, S. , GHANI, Tahir , DOYLE, Brian, S. , O'BRIEN, Kevin, P. , DOCZY, Mark, L. , OGUZ, Kaan
- 申请人: INTEL CORPORATION
- 申请人地址: 2200 Mission College Boulevard Santa Clara, California 95054 US
- 专利权人: INTEL CORPORATION
- 当前专利权人: INTEL CORPORATION
- 当前专利权人地址: 2200 Mission College Boulevard Santa Clara, California 95054 US
- 代理机构: BABBITT, William, Thomas et al.
- 主分类号: H01L43/02
- IPC分类号: H01L43/02 ; H01L43/08 ; H01L43/10 ; H01L43/12
摘要:
An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.
摘要(中):
一种装置,包括:布置在由字线和位线限定的栅格中的存储器单元阵列,存储器单元包括电阻存储器组件和存取晶体管, 其中所述存取晶体管包括相对于相关字线以锐角设置的扩散区。 一种方法包括蚀刻基板以形成多个鳍片,每个鳍片包括具有长度尺寸的主体,所述主体包括多个第一结区域和多个第二结区域,所述多个第一结区域和多个第二结区域彼此大致平行并且被成角度的沟道区域 从第二结区的起始处开始第一结区的末端; 去除间隔物材料; 并在多个鳍片中的每个鳍片的沟道区域上引入栅电极。 p>
IPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L43/00 | 应用电—磁或者类似磁效应的器件;专门适用于制造或处理这些器件或其部件的方法或设备 |
--------H01L43/02 | .零部件 |