发明申请
WO2013184880A1 USE OF CONFORMAL COATING ELASTIC CUSHION TO REDUCE THROUGH SILICON VIAS (TSV) STRESS IN 3-DIMENSIONAL INTEGRATION
审中-公开
基本信息:
- 专利标题： USE OF CONFORMAL COATING ELASTIC CUSHION TO REDUCE THROUGH SILICON VIAS (TSV) STRESS IN 3-DIMENSIONAL INTEGRATION
- 专利标题（中）：使用合适的涂层弹性垫片减少三维积分中的硅（TSV）应力
- 申请号：PCT/US2013/044451 申请日：2013-06-06
- 公开(公告)号：WO2013184880A1 公开(公告)日：2013-12-12
- 发明人： MCDONALD, John, F.
- 申请人： RENSSELAER POLYTECHNIC INSTITUTE
- 申请人地址： 110 8th Street Troy, NY 12180-3590 US
- 专利权人： RENSSELAER POLYTECHNIC INSTITUTE
- 当前专利权人： RENSSELAER POLYTECHNIC INSTITUTE
- 当前专利权人地址： 110 8th Street Troy, NY 12180-3590 US
- 代理机构： ETKOWICZ, Jacques, L.
- 优先权： US61/689,531 20120607
- 主分类号： H01L23/48
- IPC分类号： H01L23/48 ; H01L21/768 ; H01L25/065 ; H01L25/16
摘要：
Integrated circuit assemblies, as well as methods for creating the same, are provided. The integrated circuit assembly includes a first chip and a second chip, including respective face surfaces, wherein the first chip and the second chip are bonded in a face-against-face contact configuration. The integrated circuit assembly includes a via disposed to pass through the first chip and the second chip. The via is surrounded by at least one material of the respective first chip and the second chip. A cushion layer encapsulating at least a portion of the via is formed between the via and the at least one material surrounding the via.
摘要（中）：
提供了集成电路组件，以及用于创建它们的方法。 集成电路组件包括第一芯片和第二芯片，其包括相应的表面，其中第一芯片和第二芯片以面对面接触配置结合。 集成电路组件包括布置成穿过第一芯片和第二芯片的通孔。 通孔由相应的第一芯片和第二芯片的至少一种材料包围。 在通孔和围绕通孔的至少一种材料之间形成包封通孔的至少一部分的缓冲层。
IPC结构图谱:
| H | 电学 |
| --H01 | 基本电气元件 |
| ----H01L | 半导体器件；其他类目未包含的电固体器件 |
| ------H01L23/00 | 半导体或其他固态器件的零部件 |
| --------H01L23/48 | .用于向或自处于工作中的固态物体通电的装置，例如引线、接线端装置 |