发明申请
WO2011102206A1 SEMICONDUCTOR MEMORY DEVICE, DRIVING METHOD THEREOF, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
审中-公开
基本信息:
- 专利标题： SEMICONDUCTOR MEMORY DEVICE, DRIVING METHOD THEREOF, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
- 专利标题（中）：半导体存储器件及其驱动方法及制造半导体器件的方法
- 申请号：PCT/JP2011/051846 申请日：2011-01-25
- 公开(公告)号：WO2011102206A1 公开(公告)日：2011-08-25
- 发明人： TAKEMURA, Yasuhiko
- 申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD. , TAKEMURA, Yasuhiko
- 申请人地址： 398, Hase, Atsugi-shi, Kanagawa 2430036 JP
- 专利权人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.,TAKEMURA, Yasuhiko
- 当前专利权人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.,TAKEMURA, Yasuhiko
- 当前专利权人地址： 398, Hase, Atsugi-shi, Kanagawa 2430036 JP
- 优先权： JP2010-034903 20100219
- 主分类号： H01L21/8247
- IPC分类号： H01L21/8247 ; G11C11/405 ; H01L21/8242 ; H01L27/108 ; H01L27/115 ; H01L29/786 ; H01L29/788 ; H01L29/792
摘要：
A matrix is formed using a plurality of memory cells in each of which a drain of the writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor. A gate of the writing transistor, a source of the writing transistor, a source of the reading transistor, and a drain of the reading transistor are connected to a writing word line, a writing bit line, a reading bit line, and a bias line, respectively. The other electrode of the capacitor is connected to a reading word line. In order to decrease the number of wirings, the writing bit line is substituted for the reading bit line. The reading bit line is formed so as to be embedded in a groove-like opening formed over a substrate.
摘要（中）：
使用多个存储单元形成矩阵，每个存储单元中的写入晶体管的漏极连接到读取晶体管的栅极和电容器的一个电极。 写入晶体管的栅极，写入晶体管的源极，读取晶体管的源极和读取晶体管的漏极连接到写入字线，写入位线，读取位线和偏置线 ， 分别。 电容器的另一个电极连接到读取字线。 为了减少布线数量，写入位线代替读取位线。 读取位线形成为嵌入形成在基板上的槽状开口。
IPC结构图谱:
| H | 电学 |
| --H01 | 基本电气元件 |
| ----H01L | 半导体器件；其他类目未包含的电固体器件 |
| ------H01L21/00 | 专门适用于制造或处理半导体或固体器件或其部件的方法或设备 |
| --------H01L21/67 | .专门适用于在制造或处理过程中处理半导体或电固体器件的装置；专门适合于在半导体或电固体器件或部件的制造或处理过程中处理晶片的装置 |
| ----------H01L21/71 | ..限定在组H01L21/70中的器件的特殊部件的制造 |
| ------------H01L21/78 | ...把衬底连续地分成多个独立的器件 |
| --------------H01L21/782 | ....制造多个器件，每一个由单个电路元件组成 |
| ----------------H01L21/822 | .....衬底是采用硅工艺的半导体的 |
| ------------------H01L21/8222 | ......双极工艺 |
| --------------------H01L21/8234 | .......MIS工艺 |
| ----------------------H01L21/8239 | ........存储器结构 |
| ------------------------H01L21/8246 | .........只读存储器结构（ROM） |
| --------------------------H01L21/8247 | ..........电可编程序的 |